Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-10-08
2002-01-01
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S143000
Reexamination Certificate
active
06335698
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to an improved apparatus for converting analog signals into digital signals.
B. Description of the Prior Art
The three major architectures for analog-to-digital converters (ADC) are the successive approximation (SAR), flash, and pipeline analog-to-digital converters.
FIG. 1
gives approximations of the functional characteristics of each of the converter types.
The fastest of the three analog-to-digital converter architectures is the flash type of converter (also called parallel type). The conversion of the analog signal into digital form by a flash converter requires only a single cycle. As disclosed in
FIG. 1
, however, the resolution of the flash converters is generally limited to 8-bits in the current manufacturing process of such converters. The limitation on the resolution of flash converters relates to the fact that the circuitry required to implement a flash converter doubles with each 1-bit increase in resolution.
A block diagram of an exemplary flash converter is shown in FIG.
2
. The flash converter includes 2
N
−1 latching comparators
10
-(1) through
10
-(2
N
−1) (N is the converting resolution in bit of the converter), 2
N
resistors
50
-(1) through
50
-(2
N
), an input voltage V
IN
, a reference voltage V
REF
and an encoder
20
.
The input voltage to the analog-to-digital converter is coupled to the non-inverting terminal of each of the latching comparators
10
. The reference voltage V
REF
is coupled to the inverting terminal of each of the latching comparators
10
via resistive voltage divider string
40
. Voltage dividing string is comprised of 2
N
equal valued resistors
50
serially connected together between reference voltage V
REF
and ground. The serially connected resistors
50
couple 2
N
−1 different voltages V
ref
to the 2
N
−1 comparators
10
. Each of the voltages V
ref
is biased one least significant bit (LSB) higher than that of the preceding voltage V
ref-1
. If the input voltage V
IN
is higher than voltage V
ref
, comparator
10
will output a logic “1”. If the input voltage V
IN
is lower than the voltage V
ref
, comparator
10
will output a logic “0”.
The outputs from the group of comparators
10
is called a “thermometer” code. This thermometer code is subsequently converted to a conventional binary output by encoder
20
.
Implementing an 8-bit flash analog-to-digital converter in accordance with
FIG. 2
would require 255 comparators and 256 resistors for the voltage divider string. An exemplary embodiment of a comparator
10
for use in the flash converter of
FIG. 2
is shown in FIG.
3
. As shown in
FIG. 3
, comparator
10
requires at least eight transistors
110
-
1
through
110
-
8
. In order to increase the resolution of the 8-bit converter by 1 bit to a 9-bit converter, the number of comparators increases to 511 and the number of resistors increases to 512. Further, the number of transistors required to implement the 511 comparators in accordance with the comparator circuit of
FIG. 3
would be 4088. This 1-bit increase doubles the requisite chip area and power dissipation of the flash converter.
In order to reduce the number of comparators required to implement a converter, an alternative architecture flash analog-to-digital converter, called the two-step flash ADC or two-stage flash ADC, has been disclosed in U.S. Pat. Nos. 5,528,242 to Kumar and 5,420,587 to Michel. The two steps or stages performed by an exemplary 8-bit converter of this type comprise the separate determination of the four most significant bits (MSB) and the four least significant bits (LSB). The determination of the four most significant bits is performed by a four bit flash analog to digital converter called the MSB ADC
210
, which provides a gross determination of the value of V
IN
by performing a comparison against sixteen reference voltages V
ref
. The reference voltage corresponding to the transition of the output of the converters of the MSB ADC from “1” to “0” (high to low) is then coupled to a second four bit flash ADC called the LSB ADC
220
, which determines the four least significant bits of the converted signal.
The two-step or two-stage type converters reduce the number of comparators required to
2
(2
N/2
−1), but also provide reduced performance relative to the conventional flash converters. Further, although the number of comparators is reduced, the complexity of the circuitry required remains high.
SUMMARY OF THE INVENTION
The object of the invention is to provide an improved analog-to-digital converter.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises a flash analog-to-digital converter having a plurality of inverter circuits for providing a comparison of an input voltage with a plurality of threshold voltages, and an encoder for producing a digital signal from said comparison. Each of the inverter circuits comprises a programmable memory cell and a load.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and together with the description, serve to explain the principles of the invention.
REFERENCES:
patent: 4449118 (1984-05-01), Dingwall et al.
patent: 4763106 (1988-08-01), Gulczynski
patent: 5034905 (1991-07-01), Widdau et al.
patent: 5237326 (1993-08-01), Jeong
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5293560 (1994-03-01), Harari
patent: 5420587 (1995-05-01), Michel
patent: 5528242 (1996-06-01), Kumar
patent: 5668756 (1997-09-01), Tomioka
patent: 6037890 (2000-03-01), Glass et al.
patent: 6124813 (2000-09-01), Robertson et al.
Fujita et al., “A Floating-Gate Analog Memory Device for Neural Networks,” IEEE Transactions on Electron Devices (11/93), 40:2029-35.
Ong et al., “The EEPROM as an Analog memory Device,” IEEE Transactions on Electron Devices (9/89), 36:1840-41.
Jiang Hsin-Chin
Ker Ming-Dou
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Industrial Technology Research Institute
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