Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2000-08-03
2002-07-16
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
Reexamination Certificate
active
06420217
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to fuse elements used in semiconductor devices, and more particularly to an integrated fuse element capable of being programmed to high resistance in low voltage process technology.
2. Description of Related Art
Fuses are frequently used in integrated circuits to permanently store information, or to form the desired interconnections after the integrated circuit is manufactured.
A fuse
80
is shown in FIG.
1
. Fuse
80
and the corresponding programming and sensing circuitries are described in detail in the patent issued to Bohr et al. (U.S. Pat. No. 5,708,291, issued Jan. 13, 1998). The fuse device of Bohr et al. has a low programming voltage, and thus, a low programming current. This requires that the sensing circuit used to sense whether the fuse has been programmed or burned, does not burn (i.e. program) an unburned (i.e. unprogrammed) fuse in the sensing process. Further, the fuse device may exhibit only a small change in resistance between an unprogrammed state and a programmed state. Thus, Bohr et al.'s fuse requires a sensing circuit sensitive enough to detect relatively small changes in resistance to reliably determine whether the fuse has been programmed. To that end, Bohr et al. uses relatively complex reference resistance and current mirror scheme which consumes large silicon area.
Thus, a fuse structure and a method for programming the fuse is needed which enables programming the fuse to high resistance in low voltage process technologies, and allows simple circuitry which consumes minimal silicon area to be used for sensing the state of the fuse.
SUMMARY
In accordance with this invention, an integrated fuse element capable of being programmed to high resistance in a low voltage process technology is provided. The fuse includes a stack of a low resistivity material over and in contact with a high resistivity material. As part of the invention, to program the fuse, a voltage applied across the stack is increased until a first agglomeration event occurs, whereby a discontinuity is formed in the low resistivity material. The voltage is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse.
In one embodiment, the low resistivity material is silicide and the high resistivity material is undoped polysilicon.
In one embodiment, an extended-drain MOS transistor capable of sustaining high voltage is coupled to the fuse for programming the fuse. The transistor includes: a well region of a first conductivity type in a bulk region of a conductivity type opposite the well region, the well region forming the drain of the transistor; an insulating trench in the well; a polysilicon gate extending over a portion of the substrate and a portion of the trench; a first diffusion region in the well region, the first diffusion region being laterally spaced from the polysilicon layer by the trench; and a second diffusion region in the bulk region, the second diffusion region forming a source of the transistor, the first and second diffusion regions having a conductivity type opposite the bulk region.
In one embodiment, the portion of the bulk region over which the polysilicon layer extends forms a channel region; and the polysilicon layer extends over a portion of the well region, the portion of the well region including a surface region adjacent to the channel region.
In another embodiment, upon reverse-biasing the junction between the well and the bulk region a depletion region is formed which encompasses the surface region of the well adjacent to the channel region.
In another embodiment, the trench is formed to have a depth and a surface width so that a parasitic resistance between the first diffusion region and the channel region is minimized.
In another embodiment, the MOS transistor and the fuse element are serially-connected between a power supply terminal and a ground terminal, the drain of the MOS transistor being connected to the fuse element, the MOS transistor being for programming the fuse to have a higher resistance as compared to an unprogrammed fuse.
In another embodiment, the MOS transistor is coupled to both the fuse element and a sensing circuit which senses the state of the fuse. The transistor isolates a high voltage applied to the fuse from the sensing circuit. In one embodiment, the drain of the MOS transistor is connected to one end of the fuse element, and the source of the MOS transistor is connected to the sensing circuit.
In another embodiment, the transistor is a NMOS or a PMOS transistor.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
REFERENCES:
patent: 5708291 (1998-01-01), Bohr et al.
Bergemont Albert
Kalnitsky Alexander
Poplevine Pavel
Christianson Keith
National Semiconductor Corporation
Skjerven Morrill LLP
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