Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-02-28
2002-09-17
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S374000, C257S501000, C257S510000, C257S517000, C257S524000
Reexamination Certificate
active
06452246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improvement of a semiconductor device having a trench isolation structure.
2. Background Art
In accordance with miniaturization of a semiconductor element, isolation between elements has also come to be effected on a much more minute scale. A method of defining an isolation region by thermal oxidation of a silicon substrate, what is called Local Oxidation of Silicon (LOCOS), inevitably involves generation of a structural defect called a bird's beak. Thus, the LOCOS method involves a problem of the bird's beak destroying a minute active region sandwiched between the isolation regions. A widely-known approach to solve this problem is to prevent formation of a bird's beak by means of the trench isolation method.
The trench isolation method involves embedding an insulating layer in a trench formed in a silicon substrate. After the insulating layer is embedded in the trench, the film is etched to the vicinity of the primary surface of the silicon substrate. The etched surface is smoothed by means of a widely-used dry etching or chemical-and-mechanical polishing (CMP) method.
As shown in
FIG. 23
, an active region
11
and an isolation region
21
a
coexist in a semiconductor substrate
10
of an actual semiconductor device, and an embedded oxide film constituting the isolation region
21
a
is formed so as to become raised in comparison to the primary surface of the active region
11
. Reference numeral
21
b
designates a bird's beak. In this structure, as in the case of a LOCOS structure, formation of a parasitic MOS can be prevented by raising an isolation oxide film higher than the silicon substrate
10
. Further, there can be prevented a reduction in a withstand voltage with respect to a gate, which would otherwise be caused when the edge of an opening of the trench isolation structure becomes steeps.
However, such a conventional semiconductor device suffers the following problems.
FIG. 24
is a cross-sectional view showing the conventional semiconductor device as viewed from the widthwise direction of the gate. As indicated by arrows in the drawing, the effective width of the gate becomes smaller, which in turn diminishes the amount of drain current.
FIG. 25
shows another conventional semiconductor device as viewed from the widthwise direction of the gate. In such an example of the conventional semiconductor device, an n-type layer
16
is formed on, e.g., a p-type layer
15
of the semiconductor substrate
10
. In this case, a silicide layer
80
is formed close to the bird's beak
21
b
, and a junction edge of the n-type layer
16
(which is a reverse conductive layer) beneath the silicide layer
80
comes close to the silicide layer
80
. Therefore, a depletion layer is susceptible to becoming closer to the silicide, thereby resulting in a decrease in the withstand voltage of the device.
The conventional trench isolation structure as described above is likely to exhibit a so-called narrow channel effect. Specifically, the threshold voltage of the transistor is likely to increase in association with miniaturization of the semiconductor device and is prone to becoming difficult to control, which in turn results in lack of drain current or makes the semiconductor device inoperable.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the problems as associated with the conventional semiconductor device, and the object of the present invention is to provide an improved semiconductor device, and a method of manufacturing such a semiconductor device, which prevents a decrease in the amount of drain current in a transistor.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate having a primary surface, and a trench isolation region formed in the primary surface of the semiconductor substrate for separating the surface region of the semiconductor substrate into a plurality of active regions. At least a portion of the trench isolation region adjoining the semiconductor substrate is depressed by a predetermined depth with respect to the primary surface of the semiconductor device.
According to another aspect of the present invention, in a method of manufacturing a semiconductor device, a trench for a trench isolation structure is formed on a primary surface of a semiconductor substrate through a mask pattern formed on the primary surface of the semiconductor substrate. An insulating layer is formed on the primary surface of the semiconductor substrate so as to fill the trench. The insulating layer is removed substantially to the height of the primary surface of the semiconductor substrate. The mask pattern is removed. The insulating layer is removed by a predetermined depth, to thereby cause the insulating layer provided within the trench to recede from the primary surface of the semiconductor substrate by a predetermined depth thereby forming a trench isolation structure.
In another aspect of the present invention, in a method of manufacturing a semiconductor device, an insulating layer is removed at a portion adjoining the semiconductor substrate to recede from the primary surface of the semiconductor substrate by a predetermined depth thereby forming a trench isolation structure.
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patent: 6034409 (2000-03-01), Sakai et al.
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Flynn Nathan
Forde Remmon R.
McDermott & Will & Emery
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