Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1998-12-07
2002-01-22
Sheikh, Ayaz (Department: 2155)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S121000, C700S103000, C700S116000, C702S083000
Reexamination Certificate
active
06341241
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a defect analysis method for analyzing the cause of defectiveness in electric characteristics or the like of a semiconductor device which is capable of inspecting the presence or absence of defects in a product during the manufacturing process.
2. Discussion of the Invention
Conventionally, a semiconductor device such as a DRAM or a micro computer has been manufactured through a plurality of manufacturing processes. After those processes have been completed, a total defective
on-defective test on the electric characteristics has been carried out to obtain an yield of the device. On the other hand, after a specified process out of the plurality of manufacturing processes, inspection by an inspection apparatus has been carried out to detect a defect.
Now, we will describe several types of defects to be detected by the inspection apparatus. The defects include a pattern defect, a particle, adhesion of contaminants (stains), damage, or the like. The pattern defect includes short (two wires or layers to be generally isolated are short-circuited), breaking of wire (wires or layers to be generally connected are disconnected), abnormality in shape (the shape of a pattern is abnormal), or the like. A probable cause of the short or the breaking of wire is, for example, patterning with a particle used as a mask. The particle is considered to include an adhered particle, etching residual, or the like. An example of the adhesion of contaminants is adhesion of contaminants in a wet tub. The damage can occur, for example, when a handling error makes a scratch on a wafer.
In defect analysis, the influence of a specified process on the yield of the semiconductor device can be inspected by comparing the yield of the semiconductor device obtained after the manufacturing processes and the number of defects detected after the specified process.
The number of defects detected at the specified process is, however, highly unstable because it can be increased when an unusual number of defects or an aggregate defect is included in a single chip, or because it can be unreliable when the defects detected after the specified process includes a large number of defects due to previous processes. Thus, only a low-reliable correlation is available from a simple comparison between the number of defects detected at the specified process and the yield of the device. This creates a great difficulty in improving accuracy in analyzing the influence of the specified process on the yield of the device.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a defect analysis method of a device which includes an integrated circuit formed through a plurality of processes on each of a plurality of chips on a wafer. The defect analysis method comprises the steps of: (a) after each of at least one process out of the plurality of processes, detecting a new defect caused by at least one process and occurring in a new area of the wafer other than an area of a defect occurring at a previous process and its vicinity; (b) after the plurality of processes are completed, making a defective
on-defective judgment on the integrated circuit on each of the plurality of chips is; (c) judging the presence or absence of the new defect satisfying a predetermined identifying condition, for each of the plurality of chips for each of at least one process; (d) classifying the plurality of chips into four groups on the basis of a combination of the judgment of the step (b) and the judgment of the step (c), for each of at least one process; and (e) calculating the number of new defective chips considered to be caused only by the new defect of at least one process, on the basis of the fourfold classification of the step (d).
According to a second aspect of the present invention, the defect analysis method further comprises the step of: (f) calculating a critical rate of the new defect of at least one process, at which a chip is considered to become defective, on the basis of the fourfold classification of the step (d).
According to a third aspect of the present invention, the defect analysis method further comprises the step of: (g) calculating the number of process defective chips considered to be caused by at least one process, on the basis of the fourfold classification of the step (d) and the critical rate.
According to a fourth aspect of the present invention, in the defect analysis method, the step (c) is performed a plurality of times by using each of a plurality of detection sizes as a referred detection size, wherein the predetermined identifying condition includes a condition that a defect be of not less than the referred detection size; and the steps (d) to (g) are performed the plurality of times corresponding to the step (c) performed the plurality of times, so that data for analysis consisting of the number of new defective chips, the critical rate, and the number of process defective chips are obtained for each of the plurality of detection sizes for each of at least one process.
According to a fifth aspect of the present invention, the defect analysis method further comprises the step of: (h) after the steps (c) to (g) are performed the plurality of times, recognizing at least one of the following as an analysis result of at least one process on the basis of the data for analysis: an absolute critical detection size which is the minimum detection size for 100% of the critical rate out of the plurality of detection sizes; the maximum number of process defective chips out of the numbers of process defective chips obtained for each of the plurality of detection sizes; an optimum-sensitivity detection size corresponding to the maximum number of process defective chips, out of the plurality of detection sizes; and the number of optimum-sensitivity new defective chips corresponding to the optimum-sensitivity detection size out of the numbers of new defective chips obtained for each of the plurality of detection sizes.
According to a sixth aspect of the present invention, in the defect analysis method, at least one process includes a predetermined number of processes of not less than two; the data for analysis is obtained for each of the predetermined number of processes, and at the step (h), the maximum number of process defective chips is recognized for each of the predetermined number of processes. The defect analysis method further comprises the step of: (i) ranking the predetermined number of processes according to their necessity for improvement, by comparing the maximum numbers of process defective chips of the predetermined number of processes.
According to a seventh aspect of the present invention, in the defect analysis method, at least one process includes the plurality of processes; the data for analysis is obtained for each of the plurality of processes; and the step (h) includes a step of recognizing the number of optimum-sensitivity new defective chips for each of the plurality of processes. The defect analysis method further comprises the step of: (i) recognizing a degree to which the cause of defectiveness is detected, by comparing a total number of the numbers of optimum-sensitivity new defective chips of the plurality of processes, and the number of chips judged as defective at the step (b).
According to an eighth aspect of the present invention, in the defect analysis method, the device includes a plurality of devices of the same structure each manufactured through the plurality of processes of a plurality of manufacturing lines; the steps (b) to (h) are performed for each of the plurality of devices; and the step (h) includes a step of recognizing the maximum number of process defective chips of at least one process of each of the plurality of manufacturing lines. The defect analysis method further comprises the step of: (i) recognizing superiority or inferiority of the plurality of manufacturing lines by comparing the maximum numbers of process defective chips of at least one process of the plurality of
Hattori Nobuyoshi
Mugibayashi Toshiaki
Backer Firmin
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Sheikh Ayaz
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