Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-26
2002-09-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S185300
Reexamination Certificate
active
06452837
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon the prior Japanese Patent Applications No. 11-062269, filed Mar. 9, 1999; and No. 11-369758, filed Dec. 27, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a technique of controlling the threshold voltage of a nonvolatile semiconductor memory and, more particularly, to a technique of shifting the threshold voltage of an overerased cell to an appropriate threshold voltage range.
A nonvolatile semiconductor memory conventionally uses a scheme of injecting hot electrons from the drain side to the floating gate to write data in a selected memory cell (to be simply referred to as a cell hereinafter) and removing electrons from the floating gate to the source diffusion layer or to the substrate through the entire channel surface on the basis of the mechanism of a Fowler-Nordheim tunnel current to erase data. Cells constitute one block in units of, e.g., 64 kbytes (512 kbits). In the erase, data are flash-erased at once in units of blocks. The distribution of the threshold voltage of the cell in the flash erase will be described with reference to FIG.
1
.
As shown in
FIG. 1
, erase operation is repeatedly performed until the latest erased bit obtains a desired threshold voltage V
TH
. This voltage is called an erase verify voltage V
EV
. The value of the erase verify voltage V
EV
is preferably set as small as possible to increase a difference &Dgr;V between the voltage applied to a selected word line and the value of the erase verify voltage V
EV
in the data read. The larger the voltage difference &Dgr;V becomes, the larger the ON current flowed by the cell becomes. Hence, the data can be read out at a higher speed, and the performance of the nonvolatile semiconductor memory improves.
In flash erase in units of blocks, since the erase speed varies between the cells, the threshold voltage V
TH
after the flash erase varies with a certain distribution width D, as shown in FIG.
1
. The threshold voltage V
TH
varies due to various reasons, and generation or disappearance of a trap in the gate oxide film is also related. For this reason, when the rewrite is repeated, the erase speed of a cell suddenly increases or returns to the previous speed again.
When a cell (to be referred to as an overerased cell hereinafter) whose threshold voltage V
TH
becomes too low because of a high erase speed, e.g., a cell whose threshold voltage V
TH
is equal to or lower than the voltage applied to unselected word lines in the data read is generated, several problems occur in the subsequent write operation or read operation.
FIG. 2
is a circuit diagram showing the cell array of a nonvolatile semiconductor memory (flash memory).
As shown in
FIG. 2
, cells MC are arranged as a matrix in the cell array. A drain terminal D of each cell is connected to a bit line BL (BL
1
, BL
2
, BL
3
, BL
4
, . . . ) running in the horizontal direction in
FIG. 2
, and a control gate CG is connected to a word line WL (WL
1
, WL
2
, WL
3
, WL
4
, . . . ) running in the vertical direction in FIG.
2
. The source terminal of each cell is connected to a source line SL running in the vertical direction in FIG.
2
.
Problems which occur when an overerased cell is generated in the cell array will be described with reference to FIG.
3
.
FIG. 3
shows the biased state of the cell array in the write operation.
As shown in
FIG. 3
, assume that an overerased cell (e.g., a cell MC
32
in
FIG. 3
) is generated in the cell array. The overerased cell MC
32
flows an excess leakage current I
LEAK
from its drain terminal D to source terminal S. For this reason, in the subsequent operation, the excess leakage current I
LEAK
will flow to the bit line BL
2
to which the overerased cell MC
32
is connected. For example, in the write operation generally performed next to the erase operation, the excess leakage current I
LEAK
reduces the voltage of the bit line BL
2
. For this reason, when data is to be written in a cell (e.g., a cell MC
12
in
FIG. 3
) connected to the bit line BL
2
, the write time increases, or in some cases, the write is disabled.
In a recent nonvolatile semiconductor memory, the bias voltage to be applied to the bit line BL in the write operation is boosted from a low power supply voltage using a charge pump circuit. In such a nonvolatile semiconductor memory, drop of the voltage on the bit line BL particularly tends to occur due to the leakage current I
LEAK
.
Even when the write is possible, if the leakage current I
LEAK
flows to the bit line BL in the read operation, data of all cells with drain terminals connected to the bit line BL may be erroneously detected as data “1”. Even when the detection error for data “1” is avoided, the read speed from the cell with data “0” may be reduced by the leakage current I
LEAK
.
The generation frequency of such an overerased cell increases as the erase verify voltage V
EV
becomes low.
On the other hand, however, since the performance of the nonvolatile semiconductor memory can improve as the erase verify voltage V
EV
is lowered, as described above, the erase verify voltage V
EV
is required to be as low as possible.
To meet this requirement, it has been proposed to employ a function of restoring the excessively low threshold voltage V
TH
to a desired value after the flash erase.
As one method for this, the bit line BL connected to the cell whose threshold voltage V
TH
is too low is detected, and a high voltage is applied to the bit line BL while fixing the voltage of the word line WL to a potential of, e.g., almost 0 V. With this operation, the excessively low threshold voltage V
TH
is raised to a desired value. This method is disclosed in S. Yamada, IEDM Tech. Dig, pp. 307-310 (1991) and currently called a self-convergence method.
FIG. 4
shows the biased state of a cell in the self-convergence operation.
With the self-convergence method, however, when the desired threshold voltage is relatively high, a very long time is required to raise the threshold voltage V
TH
to the desired value, unlike, e.g., the normal write operation. As is apparent from data disclosed in the above reference, a time of several ms or less suffices to raise the threshold voltage V
TH
to 0 V or more, though a time of several ten ms is required to raise the threshold voltage to 1 V or more. For a recent memory cell having a short channel length, the threshold voltage rises to about −1 to 0 V in a shorter time: for example, the threshold voltage rises to about 0 V in, e.g., about 1 ms. The threshold voltage rises to −1 V in a much shorter time. However, to increase the threshold voltage to a higher level, a long time is often necessary because the speed of rise is saturated even in a microfabricated device. For this reason, when the number of cells whose threshold voltages V
TH
must be raised is large, an impractical time is required for the entire chip to increase the threshold voltages V
TH
of all the cells to a desired value of, e.g., 1 V or more using only this method.
In addition, when a plurality of overerased cells are connected to one bit line BL, a leakage current flows through the plurality of overerased cells. Hence, in the self-convergence operation, the voltage of the bit line BL drops, and only this may make the time required to boost the threshold voltage V
TH
to a desired value very long.
As another method, an overerased cell is detected by scanning the voltage of the word line WL at a predetermined voltage, the detected overerased cell is selected, and desired voltages are applied to the word line WL and bit line BL connected to the selected overerased cell to write data until the threshold voltage V
TH
rises to a desired value. This method is disclosed in U.S. Pat. No. 5,568,419 and generally called a weak-program method.
FIG. 5A
shows the biased state of a selected cell in the weak-program operation.
In this weak-program method, electrons are injected from the drain to the floating gate by positivel
Kato Hideo
Mori Seiichi
Saito Hidetoshi
Sasaki Hiroyuki
Auduong Gene N.
Kabushiki Kaisha Toshiba
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