Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-05-02
2002-04-16
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000, C327S270000, C327S276000, C327S393000
Reexamination Certificate
active
06373303
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-150254, filed May 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a sync signal generating circuit provided in a semiconductor integrated circuit such as a synchronous DRAM. More particularly, this invention relates to a sync signal generating circuit for generating an internal clock signal from an external clock signal, which internal clock signal is synchronized with the external clock signal.
In modern semiconductor integrated circuits, there is a demand for a higher input/output operation speed in an I/O section (data input/output section). In order to make the phase of data agree with that of a system clock signal, a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop) is used. Among DLLs, a mirror-type DLL is more advantageous than a feedback-type DLL since the former has a high synchronization speed.
In particular, in an ASMD (Analog Synchronous Mirror Delay) disclosed in the Journal of Solid-State Circuit, Vol. 34, No. 4, April, 1999, “An Analog Synchronous Mirror Delay for High-Speed DRAM Application”, or an analog-operable mirror-type DLL disclosed in Japanese Patent Application No. 11-228710, no such quantization error, as occurs in a digital-operable mirror-type DLL, will occur and high-precision operational characteristics can be obtained.
FIG. 1
shows an example of a conventional analog-operable mirror-type DLL. The DLL comprises an input buffer
51
, an I/O replica
52
, a comparator replica
53
, two ramp-voltage generating circuits (RVG
1
, RVG
2
)
54
and
55
, a comparator
56
, and a DQ buffer
57
.
The input buffer
51
receives an external clock signal and outputs a clock signal CLK
1
obtained by delaying the external clock signal. The I/O replica
52
receives the clock signal CLK
1
and outputs a clock signal CLK
2
, which is obtained by delaying the clock signal CLK
1
by a delay time substantially equal to a sum of a delay time in the input buffer
51
and a delay time in the DQ buffer
57
from a time point of change of an internal clock signal to a time point of outputting of DQ. The comparator replica
53
receives the clock signal CLK
2
and outputs a clock signal obtained by delaying the clock signal CLK
2
by a delay time substantially equal to a delay time in the comparator
56
.
The ramp-voltage generating circuit, RVG
1
54
, receives the clock signal from the comparator replica
53
and the clock signal CLK
1
and outputs a ramp voltage (analog voltage) Vmeans. The potential level of the ramp voltage Vmeans rises at a constant gradient in synchronism with the rising of the clock signal from the comparator replica
53
, and the rising of this potential level stops in synchronism with the rising of the clock signal CLK
1
.
The ramp-voltage generating circuit, RVG
2
55
, receives the clock signal CLK
1
and outputs a ramp voltage (analog voltage) Vdly, whose potential level rises at a constant gradient in synchronism with the rising of the clock signal CLK
1
. Assume that the gradients of the rising of the output voltages Vmeans and Vdly in both ramp-voltage generating circuits
54
and
55
are equal.
The comparator
56
compares both voltages Vmeans and Vdly and produces an internal clock signal on the basis of the comparison result. The DQ buffer
57
receives internal data and the internal clock signal, takes in the internal data in synchronism with the internal clock signal, and outputs the data as data DQ to the outside.
FIG. 2
is a signal waveform diagram illustrating an example of the operation of the DLL shown in FIG.
1
.
If the external clock signal is supplied, the clock signal CLK
1
rises with a delay tIB (input buffer delay: a delay time in the input buffer
51
) relative to the external clock signal. Then, the clock signal CLK
2
rises with a delay tREP (=tIB+tOB: tOB is a delay time in the DQ buffer
57
) relative to the clock signal CLK
1
. After a delay time in the comparator replica
53
from the rising of the clock signal CLK
2
, the output clock signal of the comparator replica
53
rises and the output voltage Vmeans in the ramp-voltage generating circuit
54
begins to rise.
If a second-cycle external clock signal rises after the lapse of a first cycle time tCLK of the external clock signal, and a second-cycle clock signal CLK
1
rises, the rising of the output voltage Vmeans of the ramp-voltage generating circuit
54
stops and, in turn, the output voltage Vdly of the other ramp-voltage generating circuit
55
begins to rise. The voltages Vdly and Vmeans are compared and, when both voltages have coincided, the internal clock signal rises. The data DQ is output from the DQ buffer
57
with a delay tOB (DQ buffer delay) relative to the rising of the internal clock signal.
Since the output voltages Vmeans and Vdly of the two ramp-voltage generating circuits
54
and
55
rise at the same gradient, a time period tRAMP from when the output voltage Vmeans of the ramp voltage generating circuit
54
begins to rise to when the rising of the output voltage Vmeans stops in synchronism with the clock signal CLK
1
is equal to a time period tRAMP from when the output voltage Vdly of the other ramp-voltage generating circuit
55
begins to rise to when the output voltage Vdly becomes equal to the output voltage Vmeans. In addition, the delay time of the comparator replica
53
is substantially equal to that of the comparator
56
. Thus, assuming that each delay time is tCMP, a delay time &Dgr;TOTAL of the data DQ relative to the external clock signal is given by
&Dgr;TOTAL=tIB+tREP+tCMP+tRAMP+tRAMP+tCMP+tOB (1)
Since tIB+tOB=tREP, it this is substited in equation (1), the following equation (2) is obtained:
&Dgr;TOTAL=2(tREP+tCMP+tRAMP) (2)
The time period tRAMP is given by the following equation (3), that is, by subtracting the sum of tIB, tREP and tCMP from the time period (tIB+tCLK) from the timing at which the first-cycle external clock signal rises to the timing at which the second-cycle clock signal CLK
1
rises:
tRAMP
=
(
tIB
+
tCLK
)
-
(
tIB
+
tREP
+
tCMP
)
=
tCLK
-
(
tREP
+
tCMP
)
(
3
)
If equation (3) is substituted in equation (2), equation (4) is obtained:
Δ
TOTAL
=
2
{
tREP
+
tCMP
+
tCLK
-
(
tREP
+
tCMP
)
}
=
2
tCLK
(
4
)
In other words, the data DQ, synchronized with the external clock signal, is output from the third-cycle external clock signal.
The comparator
56
shown in
FIG. 1
may be, for example, a dynamic-type comparator using a differential amplifier, a capacitor and inverters composed of NMOSFETs and PMOSFETs.
The comparator, such as a dynamic-type comparator using a differential amplifier, a capacitor and inverters, is an analog circuit. In general terms, there arises a variance in characteristics of an analog circuit due to a fabrication process, a voltage used and a temperature in operation (hereinafter referred to as “PVT” (i.e. Process, Voltage and Temperature)). In particular, if a digital-specific process is applied to circuit integration, a greater process variance will occur, compared to the case of using an analog-specific process. Such a PVT variance adversely affects, in particular, analog circuits and it causes a variance in characteristics.
FIG. 3
shows a delay time variation (ps) occurring when the threshold voltages (Vth) of the NMOSFETs and PMOSFETs of the dynamic-type comparator are higher (“High”) or lower (“Low”) than a specified value (“center”) and when the temperature (Temp.(° C.)) varies in a range between −10° C. and 100° C. When both the threshold voltages (Vth) of the NMOSFETs and PMOSFETs of the dynamic-type comparator are higher than the specified value (“High/High”), the delay time greatly increases. On the other hand, when both
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Luu An T.
Wells Kenneth B.
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