Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-09-18
2002-05-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C365S189090, C323S314000
Reexamination Certificate
active
06392472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage generation circuits. More particularly, the present invention relates to a voltage generation circuit that can supply power supply voltage speedily and stably with respect to the load of abrupt current consumption under low voltage operation, and the structure of a semiconductor memory device incorporating such a voltage generation circuit.
2. Description of the Background Art
Efforts have been exerted to reduce the operating voltage of LSI memories in accordance with the growing demand for operation at lower power consumption in the market. There is a great demand for the transistors in the chip to operate under a driving current lower than the external power supply voltage that is applied to the chip. This is also necessary from the standpoint of ensuring reliability of the transistor itself that is reduced in size due to the increase of the integration density.
Particularly, in a type of a memory such as a DRAM (Dynamic Random Access Memory), lowering the operating voltage is an important factor from the aspect of ensuring reliability of the dielectric film of the capacitor that becomes the capacitance accumulation portion in a memory cell.
To meet the above requirements, the upper limit of the internal power supply voltage has become lower with respect to the external power supply voltage used in the system as the development generation proceeds. To this end, a voltage down converter (VDC) is employed as the circuit to generate stable internal power supply voltage to ensure such reliability in the chip.
FIG. 22
is a circuit diagram showing a structure of a conventional analog type VDC
700
correspond to one basic structure of a VDC.
Analog VDC
700
receives a reference voltage Vref which is the target voltage of the internal power supply voltage used in the chip from a Vref generation circuit (not shown) to maintain stably a voltage int.Vcc at an internal power supply voltage node
715
.
Referring to
FIG. 22
, analog VDC
700
includes a differential amplify circuit
730
and a current control transistor
740
connected in series between an external power supply line
711
and a ground line
712
. Differential amplify circuit
730
generates at a control node Ncp a voltage which is an amplified version of the voltage difference between the voltage at internal power supply voltage node
715
and standard voltage Vref. Differential amplify circuit
730
is a current mirror amplify circuit with P type MOS transistors QPa and QPb as the load.
Current control transistor
740
connected between differential amplify circuit
730
and ground line
712
receives an activation signal ACT at its gate. ACT signal is used to control the operation of analog VDC
700
. When activation signal ACT is rendered active (H level), current is supplied to differential amplify circuit
730
. A desired operation is carried out by means of analog VDC
700
carrying out error amplification of the voltage difference between reference voltage Vref and voltage int.Vcc.
Analog VDC
700
further includes an output transistor
760
having its gate connected to control node Ncp, and connecting an external power supply line
711
with internal power supply voltage node
715
.
When int.Vcc≈Vref, the voltage at control node Ncp which is the output of differential amplify circuit
730
attains a high level. Therefore, output transistor
760
is turned off, so that current is not supplied to internal power supply voltage node
715
.
When int.Vcc<Vref, the voltage of control node Ncp is amplified towards the lower level by differential amplify circuit
730
. Output transistor
760
is turned on, so that current is supplied to internal power supply voltage node
715
through external power supply line
711
. Thus, voltage int.Vcc at internal power supply voltage node
715
can be controlled to the level of Vref which is the target voltage.
FIG. 23
is a circuit diagram showing a structure of a conventional digital type VDC
800
which is another example of a VDC.
Digital VDC
800
sets the gate voltage of the output transistor to either the H level or the L level in a digital manner, whereby the output transistor is driven.
Referring to
FIG. 23
, digital VDC
800
differs from analog VDC
700
of
FIG. 22
in that a signal conversion circuit
750
is further provided between control node Ncp and the gate of output transistor
760
. Signal conversion circuit
750
includes inverters I
1
and I
2
connected in series. Inverter I
1
has its input node connected to control node Ncp. Inverter I
2
has its output node connected to the gate of output transistor
760
.
By the above structure, a voltage of either the H or L level is applied to the gate of output transistor
760
according to the relationship between the voltage of control node Ncp and the logic threshold voltage of the inverter. Since digital VDC
800
amplifies the output of differential amplify circuit
730
to the CMOS level to switch the output transistor, a large current can be supplied speedily by output transistor
760
even if the driving current of differential amplify circuit
730
is low.
In an analog VDC
700
, although the gate voltage of output transistor
760
can be altered according to the reduction level of voltage int.Vcc to supply a current corresponding to the level of the consumed current, an output transistor
760
of a large size must be driven by the output of differential amplify circuit
730
that cannot easily take a large driving current. There was a problem that the operation in the VDC is greatly delayed.
In a digital VDC
800
, in contrast, a large amount of current can be supplied speedily even when the output signal of differential amplify circuit
730
is low since the output transistor is switched with the output of differential amplify circuit
730
amplified to the CMOS level.
However, it is to be noted that the voltage of control node Ncp which is the output of differential amplify circuit
730
varies in the range of Vn
0
to ext.Vcc where Vn
0
is the voltage of node Nn
0
in
FIG. 23
for digital VDC
800
. Since voltage Vn
0
corresponds to a level boosted by the channel resistance of current control transistor
740
from the ground voltage, the voltage generated at control node Ncp will change only within a narrow range if ext.Vcc is lowered. As a result, the output transistor cannot be turned on easily. Therefore, there is a possibility that power cannot be applied to the internal power supply voltage node speedily under the low voltage operation.
Although the conventional digital type VDC has speedy response due to its great amplification of the system, the problem of oscillation in the VDC per se and generation of overshooting and undershooting is encountered. There is a tendency that the control to supply the internal power supply voltage stably cannot be provided easily.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure of a voltage generation circuit that can supply an internal power supply voltage stably and speedily even under lowered external power supply voltage.
According to an aspect of the present invention, a voltage generation circuit receiving an external power supply voltage and maintaining an internal power supply voltage at a target voltage to supply that voltage to a load includes an external power supply line, an internal power supply voltage node, and a voltage conversion circuit.
The external power supply voltage is supplied through the external power supply line. The internal power supply voltage is output from the internal power supply voltage node. The voltage conversion circuit controls the current flow supplied from the external power supply line to the internal power supply voltage node according to a voltage deviation of the internal power supply voltage from the target voltage to maintain the internal power supply voltage at the target voltage.
The voltage conversion circuit includes a switch circuit coupled between a first voltage and an in
Kobayashi Mako
Morishita Fukashi
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