Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2001-01-08
2002-04-30
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S234000, C327S244000, C365S189070, C365S194000
Reexamination Certificate
active
06380782
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit having a clock input for an external clock signal. The integrated circuit also has an output unit. The output unit is controlled by an internal clock signal and outputs data to a data output. The integrated circuit also has a control unit to generate the internal clock signal from the external clock signal. The control unit has a phase shift unit that effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal.
An integrated circuit of this type in the form of an SDRAM (synchronous DRAM) is described in C. Kim et al.: “A 640 MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40 mW DLL Circuit for a 256 MB Memory System”, in ISSCC98/Session10/High-Speed Chip-To-Chip Connections/Paper FA 10.2. The output unit of the SDRAM is clocked with the internal clock signal which, as compared with the external clock signal, has a negative phase shift, which is generated by the control unit in the form of a DLL circuit (delay locked loop). The negative phase shift effected by the DLL makes the internal clock signal lead with respect to the external clock signal. The negative phase shift effected by the DLL is set in such a way that, taking account of the signal propagation time between the output unit and the data output, data output by the output unit are present at the data output with essentially the same phase as the external clock signal. In this way, the data output externally at the data output is in turn synchronized with the external clock signal. GB-A-2 316 208 describes a semiconductor circuit having a digital delay circuit. The latter contains a control unit for generating a timing signal from an externally supplied clock signal. The control unit has a delay circuit to generate the timing signal. A comparison circuit compares the phase angle of an output signal with the phase angle of a reference signal. From this comparison, a control unit sets the delay in the delay circuit.
In U.S. Pat. No. 5,550,783, Stephens, Jr. et al. describe a circuit for correcting a phase shift for a monolithic RAM memory. This has a phase correction circuit that is used to generate an internal clock signal. The phase correction circuit has a comparator circuit. An external clock signal and an internal clock signal are supplied to the comparator circuit. The external clock signal and the internal clock signal are delayed with respect to the comparator. From these two signals, a control signal is derived for the purpose of appropriate adjustment of the delay of the internal clock signal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and, in which, data is output at the data output with improved synchronism in relation to the external clock signal, irrespective of the external wiring of the circuit.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated circuit. The integrated circuit includes a clock input for an external clock signal. The clock input has a clock output unit controlled by an internal clock signal. The clock output unit outputs data to a data output during a normal mode of operation.
The integrated circuit also includes a control unit. The control unit generates the internal clock signal from the external clock signal. The internal clock signal has a specific phase shift with respect to the external clock signal. The control unit includes an adjustable phase shift unit outputting a phase shift unit output signal. The adjustable phase shift unit sets the specific phase shift of the phase shift unit output signal during a test mode of operation. A detector unit has a detector output unit and a comparison unit. The detector unit determines a capacitive load on a data output in the test mode of operation and supplies the phase shift unit with a corresponding detector signal with which the phase shift unit sets the specific phase shift. The detector output unit outputs a test signal to the data output in the test mode of operation. The comparison unit has a first comparison unit input and a second comparison unit input determining a phase shift between the external clock signal and the test signal established at the data output in the test mode of operation.
The integrated circuit also includes a first input driver. The first input driver has a first input driver input and a first input driver output. The first input driver supplies the external clock signal. The first input driver input connects to the clock input and the first input driver output connecting to the first comparison unit input of the comparison unit and to a clock input of the output unit. The first input driver forms a propagation time of the external clock signal through the first input driver.
The integrated circuit also includes a second input driver. The second input driver has a second input driver input and a second input driver output. The second input driver input is supplied with the test signal established at the data output in the test mode of operation. The second input driver output connects to the second comparison unit input of the comparison unit. The second input driver defines a propagation time of the test signal through the second input driver. The second input driver supplies data to be applied externally to the integrated circuit during the normal mode of operation.
In the integrated circuit, the propagation time of the external clock signal through the first input driver and the propagation time of the test signal through the second input driver are essentially identical.
In accordance with another feature of the invention, the output unit is controlled by the external clock signal in the test mode of operation. In addition, the control unit sets the phase shift unit so that the specific phase shift essentially equals the phase shift determined by the comparison unit.
In accordance with another feature of the invention, the integrated circuit includes a voltage controlled delay element and a phase detector unit. The voltage controlled delay element generates the internal clock signal from the external clock signal. The phase detector unit controls the voltage controlled delay element having a first phase detector unit input and a second phase detector unit input. The first phase detector unit input receives the external clock signal. The second phase detector unit input receives an output signal from the phase shift unit. The phase shift unit receives the internal clock signal. The phase shift unit effects a phase shift in the phase shift unit output signal with respect to the internal clock signal based on the detector signal.
The integrated circuit according to the invention has a clock input for an external clock signal and an output unit. The clock input is controlled by an internal clock signal in a normal mode of operation. The clock input outputs data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has an adjustable phase shift unit with which the specific phase shift can be set in a test mode of operation. The control unit also has a detector unit to determine the capacitive load on the data output in the test mode of operation. The unit supplies the phase shift unit with a corresponding detector signal on the basis of which the desired value of the phase shift is set.
The SDRAM described by Kim et al. in the aforementioned article has the disadvantage that the negative phase shift, effected by the DLL, of the internal with respect to the external clock signal leads to the desired result only for specific connections to the data output. This is because, in the invention explained below, the inventor has determined that, depending on the connection of the data output, its capacitive load can var
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Luu An T.
Stemer Werner H.
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