Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-09-30
2002-05-14
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S747000, C438S754000
Reexamination Certificate
active
06387821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multi-layer interconnection connecting an upper wiring and a metal wiring made of a copper type metal material, through a via hole.
2. Description of the Relates Art
A representative example of the conventional process for production of a semiconductor device having a multi-layer interconnection is described with reference to
FIGS. 5
to
8
. This example is a so-called dual damascene process wherein a lower wiring and an upper wiring are each formed so as to have a damascene interconnection.
On a semiconductor substrate (not shown) on which a device (e.g. transistor) has been formed, are formed a silicon oxide film
201
having a thickness of 100 nm and a HSQ (hydrogen silsesquioxane) film
202
having a thickness of 400 nm. Successively, thereon is formed a photoresist mask
203
having a predetermined pattern [FIG.
5
(
a
)]. Dry etching is conducted using this mask to form, in the HSQ film
202
, a groove for formation of buried lower wiring. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the photoresist mask
203
[FIG.
5
(
b
)]. conducted to peel the photoresist mask
203
[FIG.
5
(
b
)].
Next, on the whole surface of the resulting substrate is formed, by sputtering, a TiN
204
film (thickness: 50 nm) as a barrier metal film. Thereon is formed a copper film
205
by sputtering, to fill the groove [FIG.
5
(
c
)]. Successively, CMP (chemical mechanical polishing) is conducted to remove the unnecessary portions of the TiN film
204
and the copper film
205
, formed outside the groove, to complete a lower wiring [FIG.
5
(
d
)].
After the formation of the lower wiring, an HSQ film
206
having a thickness of 1,200 nm is formed by coating and subsequent firing. Thereon is formed a resist mask
207
having a pattern of via holes (diameter: 0.25 &mgr;m) [FIG.
6
(
a
)]. Dry etching is conducted using this resist mask
207
to form part of a via hole in the HSQ film
206
. The dry etching is stopped before the bottom of the via hole formed reaches the copper film
205
. As the etching gas, there is used, for example, a mixed gas containing C
4
F
8
and Ar, or a mixed gas further containing O
2
. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the resist mask
207
[FIG.
6
(
b
)].
Next, a resist mask
208
is formed on the HSQ film
206
[FIG.
7
(
a
)]. The width of opening of the resist mask
208
is made larger than the diameter of the resist mask
207
of FIG.
6
(
a
). Dry etching is conducted using this resist mask
208
, to form a hole having a T-shaped section in the HSQ film
206
. As the etching gas, there is used, for example, a mixed gas containing C
4
F
8
and Ar, or a mixed gas further containing O
2
. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the resist mask
208
[FIG.
7
(
b
)].
Next, on the whole surface of the resulting substrate is formed, by sputtering, a TiN film
209
(thickness: 50 nm) as a barrier metal film. Thereon is formed a copper film
211
by sputtering, to fill the hole having a T-shaped section [FIG.
8
(
a
)]. Successively, the unnecessary portions of the TiN film
209
and the copper film
211
, formed outside the hole are removed by CMP to complete an upper wiring (corresponding to the top of the T-shaped hole) and a via plug [FIG.
8
(
b
)].
In the above-mentioned conventional production process, however, there have been cases that a leakage current flows in the inter-layer insulating film formed or the device (e.g. transistor) formed beneath the inter-layer insulating film causes malfunctioning.
The present inventor made an in-depth study on the causes of such phenomena and found out that contaminants consisting of copper and copper compounds remain on the inner walls of the via hole and groove for buried wiring both formed in the inter-layer insulating film and these contaminants cause the above phenomena.
In etching the inter-layer insulating film formed on a lower wiring, to form a via hole,the necessity of overetching invites partial etching of the copper constituting the lower wiringand generates metal contaminants. These metal contaminants ordinarily adhere to the inner walls of via hole, etc. in the form of a compound formed by a chemical reaction of copper with an etching gas component. The contaminants are impossible to remove by conventional cleaning using, for example, a cleaning solution containing an amine compound; therefore, formation of barrier metal film on inner walls of via hole, etc. is inevitably conducted in a state that the contaminants remain on the inner walls of via hole, etc. The contaminants remaining on the inner walls of via hole, etc., when placed in an electric field or heated, diffuse into the inter-layer insulating film, causing various problems such as current leakage and the like.
The phenomena are explained with reference to FIG.
9
. In
FIG. 9
, on a silicon substrate
223
is formed a MOSFET comprising a source region
225
, a drain region
226
and a gate electrode
224
. The source region
225
is connected to a lower wiring consisting of a copper film
205
, via a contact hole
221
. This lower wiring is connected to a via hole
211
(including an upper wiring) consisting of a tungsten film. To the inner walls of the via hole and the buried wiring both formed in an HSQ film
206
adhere the metal contaminants
212
formed by the partial etching of the copper film
205
constituting the lower wiring. The metal contaminants
212
, when undergoing heat history or placed in an electric field, migrate like the arrow marks shown in
FIG. 9
, reach a device (e.g. transistor) and allow the device to malfunction, or stay in the inter-layer insulating film and generate a leakage current.
These problems do not appear when aluminum is used as a material for wiring, but appear when a copper type metal is used as a material for wiring. It is because copper, as compared with aluminum, is significantly large in diffusion rate in insulating film.
To form a multi-layer. interconnection free from the above problems, it is necessary to conduct, after the formation.of a via hole and a buried wiring, cleaning which is different from conventional cleaning using, for example, a cleaning solution containing an amine compound. Since such cleaning aims at (1) cleaning the inside of via hole, (2) removing the metal contaminants which have adhered on the exposed surface of inter-layer insulating film, and (3) removing the metal contaminants which have adhered after dry etching, the cleaning has requirements different from those in the other steps of semiconductor device production. Description is made on this below.
Firstly, the above cleaning aims at cleaning the inside of via hole. Therefore, the shear force of the flow of cleaning solution does not easily reach the inside of via hole which is an area to be cleaned. Substantially no shear force is produced there particularly when the via hole formed has a small diameter. Thus, no physical cleaning action is expected and it is necessary to conduct sufficient cleaning by chemical cleaning action alone.
If mismatching of photoresist occurs at the time of via hole formation, there are cases that the portion of the HSQ film contacting with the lower wiring and facing the formed via hole, formed as a result of the mismatching is etched and a slit is formed at the portion (FIG.
16
). In such a slit, no circulation of cleaning solution hardly takes place and cleaning under very sever conditions is necessary.
Secondly, the above cleaning aims at removing the copper type metal contaminants which have adhered on the exposed surface of inter-layer insulating film. Therefore, there naturally is a
Rosenman & Colin LLP
Tran Binh X
Utech Benjamin L.
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