Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-10-20
2002-05-21
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S690000, C257S692000, C257S666000, C257S669000, C257S735000, C257S784000, C257S787000
Reexamination Certificate
active
06392295
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to techniques for manufacturing a semiconductor device and, more particularly, to techniques effective in application to the prevention of transformation (e.g. camber) of a sealing member of a LOC (lead-on-chip) which having a semiconductor chip provided with inner portion of leads arranged on a main surface thereof.
BACKGROUND OF THE INVENTION
The inventors of the present invention examined the following techniques during studies for making the present invention.
In a semiconductor device on which an LSI (large-scale integration) chip is mounted, a semiconductor device called LOC is known as a semiconductor device in which a package size is reduced.
In the LOC, end portions of inner parts of leads are arranged on a main surface, i.e., a surface provided with a circuit, of a semiconductor chip, and bonding portions of the end portions of the inner parts are electrically connected to the corresponding bonding pads of the semiconductor chip by means of wire for bonding.
The semiconductor chip is bonded to end portions of the inner parts of the leads with an insulating tape or the like and is supported by end portions of the inner parts of the leads.
The semiconductor chip, the inner parts of the leads and the bonding wires are sealed in a sealing resin to form a sealing member (i.e. package).
In recent years, efforts have been made for chip shrinking for cost reduction and a LOC having a region of a relatively large area around the semiconductor chip is occurred. In the LOC, because the size of the semiconductor chip is small, only leads (first leads) are arranged on the main surface of the semiconductor chip, and leads (second leads) have inner parts terminating near the semiconductor chip.
In the LOC having the second leads not arranged on the main surface of the semiconductor chip, the inner parts of the second leads affect adversely resin balance, i.e., a state of distribution of a resin in regions on the opposite sides of the inner parts, when sealing the semiconductor chip in a sealing member by molding and, sometimes, the sealing member transforms.
When the semiconductor chip is shrunk, a portion of the sealing member extending in regions around the semiconductor chip becomes large and regions in which resin balance is unsatisfactory increase.
A LOC intended to ensure the uniform flow of a resin when forming a sealing member to prevent the sealing member from transformation is mentioned in Japanese Patent Laid-Open No. 9-116074. This LOC is provided with a branch lead branched from a lead and provided with resin balancing parts.
SUMMARY OF THE INVENTION
In the LOC disclosed in Japanese Patent Laid-Open No. 9-116074, the resin balancing parts are formed only on the branch leads branching from the leads, and are formed only in middle portions of the area outside the chip along the long sides of the semiconductor chip.
Accordingly, portions of the sealing member corresponding to regions around the semiconductor chip, i.e., portions of the sealing member corresponding to regions along and outside the long sides and the short sides of the semiconductor chip, increases with the progress of chip shrinking. Consequently, the transformation of the sealing member cannot be prevented when the resin balancing parts are disposed only in the regions outside of the long sides of the semiconductor chip.
Long bonding wires are necessary to connect the leads not disposed on the main surface of the semiconductor chip to the corresponding bonding pads by wire bonding. Such long wires are subject to wire flow during molding, and the flowed bonding wires deteriorates the performance and reliability of the semiconductor device.
The leads (second leads) not overlying the main surface of the semiconductor chip extend on a level (a level left from the semiconductor chip) higher than that on which the leads (first leads) arranged on the main surface of the chip extend, therefore, portions of the sealing member overlying the second leads are thin and it is possible that the bonding wires are exposed from the sealing member, and the second leads and the bonding wires can be seen through the sealing member.
Accordingly, it is an object of the present invention to provide a semiconductor device, in a LOC semiconductor device having leads not overlying the semiconductor chip, to prevent transformation of a sealing member, and having improved ability and reliability, and to provide a process for manufacturing such a semiconductor device.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner portions placed on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip, the inner parts of the leads and the bonding wires therein; wherein each of the inner parts of the second leads sealed in the sealing member has a bending portions of the inner part and falling substantially in a direction from the main surface toward the back surface of the semiconductor chip.
When forming the sealing member of the semiconductor device by molding, resin balance between portions of the sealing member on the upper and the lower side of the second leads is satisfactory, so that the transformation of the sealing member of the LOC having the shrunk semiconductor chip can be prevented.
According to a second aspect of the present invention, a semiconductor device comprises: a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner portions placed on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip, the inner parts of the leads and the bonding wires therein; wherein each of the inner parts of the second leads sealed in the sealing member has a high portion extending on a level above the main surface of the semiconductor chip and a low portion extending on a level below the main surface of the semiconductor chip, and the total area of the low portions of the inner parts of the second leads is greater than that of the high portions of the same.
According to a third aspect of the present invention, a semiconductor device comprises: a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions placed on the main surface of the semiconductor chip and a plurality of second leads having connecting parts terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip, the inner parts of the leads and the bonding wires therein; wherein some of the first leads and the second leads have first bending portions of the inner parts and falling substantially in a direction from the main surface toward the back surface of the semiconductor chip, and each of the same first leads respectively having the first bending portions has a second bending portion rising substantially in a direction from the back surface toward the main surface of the semicondu
Iwaya Akihiko
Masuda Masachika
Wada Tamaki
Mattingly Stanger & Malur, P.C.
Thai Luan
Thomas Tom
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