Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-28
2002-04-09
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S724000, C438S725000, C438S734000, C438S740000, C216S079000
Reexamination Certificate
active
06368979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of a dual damascene structure comprising trenches and vias in low dielectric constant (low k) dielectric material. More particularly, this invention relates to a process for forming a dual damascene structure comprising patterns of trenches and vias respectively formed in layers of low k dielectric material of an integrated circuit structure while mitigating damage to the low k dielectric material during removal of the photoresist masks used in the formation of the respective trenches and vias of the dual damascene structure.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of interconnects, including metal interconnects, being placed closer together, as well as reduction of the horizontal spacing between metal lines on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is then annealed to remove moisture. Such carbon-containing silicon oxide insulating materials formed in this manner, sometimes referred to as low k carbon-doped silicon oxide dielectric material, exhibit good gap-filling capabilities and at the same time are characterized by a dielectric constant less than 3.0 and remain stable during subsequent annealing at temperatures of up to 500° C.
However, it has been found that such carbon-doped silicon oxide dielectric material is more sensitive than conventional undoped silicon oxide to process procedures or systems subsequently carried out during formation of the integrated circuit structure. For example, the low k carbon-doped silicon oxide dielectric material has been found to be easily damaged by the conventional O
2
-based ashing system used to remove photoresist masks after vias or contact openings are formed through the low k dielectric material. While upper and lower capping layers of conventional undoped SiO
2
can be applied below and above the layer of carbon-doped silicon oxide dielectric material, to respectively protect the lower and upper surfaces of the low k material, this does not protect the freshly exposed sidewall surfaces of newly formed vias or contact openings etched through the layer of low k carbon-doped silicon oxide dielectric material. The carbon-silicon bonds in the low k carbon-doped silicon oxide dielectric material are more easily attacked and broken by the oxygen atoms utilized in the ashing treatment than are the silicon-oxygen bonds in conventional undoped silicon oxide dielectric material, resulting in via “poisoning” wherein filler materials used to fill such damaged vias does not properly adhere to the via surfaces.
Many of the same reasons for turning to the use of dielectric materials having lower dielectric constants, e.g., for increased performance, including speed, have also led to the increased use of copper instead of aluminum or tungsten in the formation of metal interconnects, as well as via filler material, for integrated circuit structures. However, while a layer of aluminum interconnects may be easily formed by depositing a layer of aluminum metal over a dielectric layer of an integrated circuit structure, followed by patterning of the aluminum layer through a mask to form aluminum interconnects, and subsequent deposition of dielectric material in the spaces between the metal interconnects, layers of copper interconnects are not so easily formed. This is due to difficulty in patterning (etching) of a previously deposited copper layer. This has lead to the development of a process commonly known as the damascene or dual damascene process.
In the damascene process the dielectric material which will separate the copper interconnects is first deposited as a dielectric layer in which trenches are then formed (usually through the entire thickness of the dielectric layer), corresponding to the desired pattern of copper interconnects. A layer of copper is then deposited over the patterned dielectric layer and into the trenches, filling them completely. All surface copper is then removed, e.g., by chemical mechanical polishing (CMP), leaving the desired pattern of copper interconnects in the trenches. When this same process is combined with the forming of openings (vias) in a lower dielectric layer to form copper-filled vias therein, followed by filling of both vias and trenches with copper, usually in a single deposition step, the process is referred to as a dual damascene process.
While the use of copper-filled vias and copper interconnects, formed in layers of low k carbon-doped silicon oxide dielectric material by the dual damascene process, would be useful, the sensitivity of the low k carbon-doped silicon oxide dielectric material to the ashing process used to remove the photoresist mask is exacerbated when copper vias and interconnects are formed in such low k carbon-doped silicon oxide dielectric material. This is because the conventional dual damascene process involves the use (and removal) of two photoresist masks, one to define the vias formed in a lower layer of low k carbon-doped silicon oxide dielectric material, and another photoresist mask to define the trenches in an upper layer of low k carbon-doped silicon oxide dielectric material, thus increasing the possibility of damage to the low k carbon-doped silicon oxide dielectric material during removal of the two photoresist masks.
It would, therefore, be desirable to provide a process wherein copper interconnects and copper-filled vias could be formed in low k carbon-doped silicon oxide dielectric material without causing damage to the low k carbon-doped silicon oxide dielectric material during the removal of the photoresist masks used to define the patterns of trench openings and vias formed in the low k carbon-doped silicon oxide dielectric material.
SUMMARY OF THE INVENTION
The invention comprises a dual damascene structure of vias and trenches formed using layers of low k carbon-doped silicon oxide dielectric material, and a process for making same, wherein a pattern of via openings and a pattern of trench openings can be respectively formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k carbon-doped silicon oxide dielectric material.
The improved process of the invention comprises: forming a first layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k carbon-doped silicon oxide dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch
Catabay Wilbur G.
Wang Zhihai
Zhao Joe W.
LSI Logic Corporation
Powell William A.
Taylor, Esq. John P.
LandOfFree
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