Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-12-17
2002-01-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S122000, C438S083000, C257S700000, C257S697000, C257S698000, C257S701000, C257S778000
Reexamination Certificate
active
06342398
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the testing of semiconductor devices, and more specifically to plastic packaged modules. The present invention relates to a method of opening the plastic packaged modules to access the semiconductor chip for chip analysis. The method of the present invention is applicable to plastic packaged modules even where the semiconductor chip is molded in a plastic encapsulating resin which is resistant to known etching techniques.
(2) Description of the Prior Art
The ability to remove encapsulated chips from a plastic package is required for various purposes, for instance for failure analysis of the encapsulated chip. Identification of the cause of failure of an encapsulated chip requires that the method of removing the chip from the encapsulating package does not effect the integrity of the chip and of the metallic interconnections to the chip. In a similar manner is it often required to physically evaluate semiconductor devices for product reliability, physical design and device structural patterns.
The quality of the chips that are removed from the encapsulating package is of prime importance in instances where the chips, which have been removed from the encapsulating package, need to be available for re-use after the chip analysis is completed.
In addition to aspects of chip functionality, the testability of the chip is also of concern. The method which is used to remove the chip from the package must not affect the functionality of the chip and must also assure that the chip remains in good condition and can be tested.
In sum, the basic problem to be addressed is to provide a method of gaining access to an encapsulated chip such that the physical and electrical integrity of the chip are maintained.
Wet chemical methods can be used to remove chips from the chip package. These methods however present problems because materials used for the wet process have a detrimental effect on chip functionality. At times very hard, etch resistant plastic resins are used as the molding compound for encapsulating a chip. The complete removal of this plastic resin without damaging the chip is a very difficult task because hard plastic resin cannot be attacked by an acid based wet process.
Another method of removing the chip from the package is to mechanically grind the chip-encapsulating package from the front side of the package, that is the side opposite to the side that exhibits the contact points or balls of the BGA. Emission microscopy allows for identifying sites within an integrated circuit where photons are generated due to the recombination of electrons with holes. Using emission microscopy the Integrated Circuit can therefore be analyzed for leakage sites within the integrated circuit.
The disadvantage of the latter method is that overlaying large metal lines within the structure of the chip may block the emission or leakage sites, these leakage sites may therefore remain undetected.
An alternate method of removing a chip from the chip encapsulation is to mechanically grind the chip encapsulation from the backside of the package. The backside of a BGA chip package is the side which is oriented towards the contact ball grid of the package. After the encapsulating layer has been removed in this manner down to the level of the ball bonds (also referred to as first bond) within the BGA, a socket is applied to the ball bonds. Electrical contact with the chip is established by means of this socket and through the ball bonds of the chip. In this way backside emission analysis, for instance, can be performed.
The disadvantage of this method is that it is very difficult to control the grinding process to the point where the ball bonds are not damaged while the bonding or contact wires which are attached to the ball bonds are also prone to be damaged during the grinding process. Also, using this approach, the chip die has to be exposed from the backside of the BGA chip by grinding underneath the die. This poses a problem if a BGA chip signal ball is located under the die and can therefore not be electrically contacted during subsequent procedures.
FIG. 1
shows a Prior Art cross section of the BGA device. The BGA die
14
is mounted in a plastic mold
16
. The backside
22
of die
14
is oriented toward the printed circuit board
12
and the contact balls
10
. The top side
24
of die
14
is facing away from the printed circuit board
12
or, which is the same thing, toward the bulk of the plastic mold
16
. Wires
18
connect contact points in the top
24
of the die
14
with contact points
20
in surface
26
. Cross section 2-2′ is further explained under
FIG. 2
following.
Points of electrical contact
28
between the die
14
and the printed circuit board
12
that are contained within the die are the first bond or ball bond contact points.
Points of electrical contact
20
between the top
24
of the die
14
and the printed circuit board
12
are the second bond or wedge bond contact points.
FIG. 2
further illustrates the above. It shows a top view of a cross section taken along line
2
-
2
′ of FIG.
1
. This cross section is directly through the top surface
24
(
FIG. 1
) of the BGA die
14
and is looking in the direction of the printed circuit board
12
. Contact pads (not shown) in surface
24
of the BGA die
14
, these contact pads are connected by wires
18
, which run within the chip molding
16
(
FIG. 1
) to the wedge bonds
20
. The wedge bonds
20
are in the backside surface (the surface facing the BGA printed circuit board
12
) of the molding
16
.
The present invention addresses the above indicated problems and limitations of accessing a BGA chip for chip analysis and provides for a reliable method of detecting leakage sites within BGA integrated circuits by performing the leakage site detection from the backside of the BGA chip.
U.S. Pat. No. 5,424,254 (Damiot) shows a method of polishing the plastic encapsulating resin in order to expose conductors. However, this reference differs from the present invention.
U.S. Pat. No. 5,570,033 (Staab) disclose a probe to test BGA's.
U.S. Pat. No. 5,712,570 (Heo et al.) shows a method for checking the bonds in a BGA by means of an electrical process.
SUMMARY OF THE INVENTION
It is the primary objective of the present invention to provide a method for electrically accessing semiconductor chips within plastic encapsulated modules which is not detrimental to the chip functionality and testability.
It is another objective of the present invention to provide a method for electrically accessing semiconductor chips within plastic encapsulated modules which preserves the terminal connection system integrity.
It is another objective of the present invention to provide a method for electrically accessing semiconductor chips within plastic encapsulated modules which is applicable to any type of plastic encapsulating resin.
It is another objective of the present invention to provide a method for electrically accessing semiconductor chips within plastic encapsulated modules which is simple to execute and which is inexpensive.
It is another objective of the present invention to provide a method for electrically accessing semiconductor chips within plastic encapsulated modules which does not cause any contamination to the accessed chip and to any used or related semiconductor processing equipment.
According to the present invention, a wax mold, which forms a chip-supporting carrier, is provided. A box sized opening is created in the wax mold, this opening is slightly larger in size than the size of the BGA IC. The BGA IC is inserted into the created opening with the backside of the BGA chip facing upward or away from the chip-supporting carrier. The BGA device backside is now polished, this polishing creates an opening in the BGA package that is slightly larger than the size of the die that is mounted within the package. This opening therefore exposes the backside of the BGA die. Next the silicon substrate of the BGA die is polished. The critical
Ackerman Stephen B.
Niebling John F.
Saile George O.
Stevenson Andre′ C
Taiwan Semiconductor Manufacturing Company
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