Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-08-23
2002-03-26
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S141000
Reexamination Certificate
active
06362762
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to analog to digital converters (ADCs). More particularly, the present invention relates to ADCs that support both wide and narrow frequency bands.
BACKGROUND OF THE INVENTION
A number of Radio-Frequency (RF) applications, such as digital radar systems, require analog-to-digital converters that will support challenging requirements for bandwidth, resolution, and dynamic range. A typical application may require analog-to-digital conversion for analog signals within one of several different 10 MHz bandwidths at a resolution of 15 signal-to-noise-and-distortion (SINAD) bits and analog-to-digital conversion for analog signals over a 1 GHz bandwidth at a resolution of 9 bits. Each separate bandwidth is considered a separate mode of analog-to-digital conversion. Each mode can be provided by separate analog-to-digital converters, but to reduce power, area, and cost, it is desired that the analog-to-digital converter units be highly integrated.
Analog to digital data conversion involves quantization of the analog input signal. Quantization required for analog to digital conversion may be multi-level quantization as illustrated in
FIG. 1A
or two-level quantization as illustrated in FIG.
1
B. The quantization process is described by the equation
y=Gx+e
G is the slope of the straight line going through the centers of the quantization steps and e is the quantization error or quantization noise. In
FIG. 1A
, the slope is indicated by the diagonal line
100
and the quantization steps are indicated by stair-step line
101
. In the two-level quantizer shown in
FIG. 1B
, the slope is indicated by the diagonal line
102
, and the two quantization levels are shown by the two-state line
103
. The error term e can be modeled as random additive noise with a uniform amplitude distribution, which has an impact on the performance of the analog-to-digital converter.
One method for reducing the quantization noise is through oversampling. It is well known that to recover a sampled analog signal, the signal must be sampled at a rate greater than or equal to twice the signal frequency, otherwise known as the Nyquist sampling rate. Oversampling refers to sampling the signal at a rate much greater than twice the signal frequency.
FIG. 2A
shows the magnitude of quantization noise, in terms of the signal-to-noise (SNR), at a particular frequency of interest f when the analog signal is sampled at the minimum sampling rate of f
s
.
FIG. 2B
shows the magnitude of quantization noise at the same frequency of interest when the signal is sampled at a sampling rate equal to 2f
s
. By comparing the quantization noise in FIG.
2
A and
FIG. 2B
, respectively, one can see that increasing the sampling frequency spreads the quantization noise over a larger bandwidth because the total quantization noise remains the same over the different sampling bandwidths. Thus, increasing the sampling rate relative to twice the signal frequency, or oversampling, reduces the quantization noise in the bandwidth of interest.
A common architecture for analog-to-digital converters that support high frequency quantization rates is a flash architecture as illustrated in FIG.
3
. In
FIG. 3
, 2
n
−1 comparators
110
are used to directly measure an analog signal
113
to a resolution of n bits. The outputs from the multiple comparators simultaneously present 2
n
−1 discrete digital output states, which are then level decoded
111
into a binary form
112
. The flash architecture is very fast, and thus has the advantage of easily operating at the quantization rates required to meet Nyquist sampling rate requirements for extremely high frequency analog signals. However, the flash architecture requires many comparators for high bit resolution, with a corresponding increase in power, size, and circuit complexity. For example, a 9-bit flash analog-to-digital converter would require 511 comparators, while a 15-bit flash analog-to-digital converter would require 32767 comparators. Hence, the large number of comparators required for high resolution is a major limitation for a flash analog-to-digital converter.
Resolution of a flash analog-to-digital converter is also limited by its quantization noise performance. The effective resolution or effective number of bits (ENOB) of the analog-to-digital converter is given by:
ENOB
=
SNR
-
1.76
dB
6.02
dB
.
If only the effect of quantization noise is considered, the effective number of bits is equivalent to the signal-to-noise and distortion (SINAD) bits. As described above, the quantization noise will the highest and, therefore, the SNR will be the lowest when the ADC is operating at the Nyquist sampling rate. If oversampling is used, the quantization noise will decrease and the SNR will increase, thus providing additional resolution. However, when only over-sampling is used to increase resolution, the sampling frequency must increase by a factor of 2
2N
to obtain an N-bit increase in SINAD resolution. Hence, each doubling of the sampling frequency can only achieve a 0.5 bit increase in SINAD resolution. Thus, a high resolution flash analog-to-digital converter incurs a bandwidth penalty for increased resolution.
A delta-sigma modulator achieves additional SINAD bits with less of a bandwidth penalty by combining over-sampling with a noise-shaping technique. A basic block diagram of a delta-sigma modulator is shown in FIG.
4
A. The delta-sigma modulator comprises a summing node
120
, an integrator
121
and a quantizer
122
coupled together in succession. A feedback loop
124
couples the Output Y(i) of the quantizer
122
to the summing node
120
through a digital-to-analog converter
123
. In operation, an analog input signal enters the summing node
120
where an analog version of the feedback signal Y
a
(i) is subtracted from it to create a difference signal X
d
(t). The difference signal is then input to the integrator
121
that produces an integral signal X
i
(t). The quantizer then rounds the integral signal X
i
(t) to the nearest quantization level thereby producing a digital signal Y
i
. The feedback loop
124
forces the average output of the quantizer to track the input signal X(t) and thus provide a digitized version of the analog input signal.
In a delta-sigma modulator, the integrator, which is a low pass filter, acts to push the quantization noise up in frequency. This feature is explained by referencing the discrete time model of the delta-sigma modulator shown in
FIG. 4B. A
sampled version of an analog signal, X(i), enters the summing node
120
where the feedback signal Y
a
(i) is subtracted from it to create the sampled difference signal X
d
(i). The integrator
121
is implemented with a discrete time integrator comprising a delay element
126
and a feedback element
127
. The integrator
121
produces an integral signal X
I
(i). The quantizer
122
is modeled as a noise source E(i) coupled to summing node
128
. Moreover, the digital-to-analog converter
123
can be treated as ideal, and modeled as a unity gain transfer function.
The output of the discrete time delta-sigma modulator can be written as
Y(i)=X
I
(i)+E(i)
where X
I
as the output of the discrete time integrator can be written as:
X
I
(i)=X(i−1)−E(i−1)
Thus,
Y(i)=X(i−1)+(E(i)−E(i−1))
In the z-domain, the output is given by
Y(z)=X(z)z
−1
+E(z)(1−z
−1
)
Thus, the transfer function for the input signal, H
x
(z) is equal to z
−1
and the transfer function of the noise source, H
n
(z) is equal to (1z
−1
). Since zero frequency is represented in the z domain at z=1, it can readily be seen that as the frequency approaches zero, E(z) is attenuated. Therefore, the integrator in the delta-sigma modulator provides that the delta-sigma modulator acts as a high pass filter for quantization noise, and a lowpass filter for the input signal.
The example above shows a first order delta-sigma modulator, where only a single
Jensen Henrik T.
Raghavan Gopal
HRL Laboratories LLC
Williams Howard L.
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