Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-05-17
2002-01-29
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S706000, C438S723000, C438S724000, C438S740000
Reexamination Certificate
active
06342449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which includes an etching process for etching a silicon oxide film using a silicon nitride film as a stopper.
2. Description of the Related Art
With the miniaturization of semiconductor devices, the dimensions of the structure of a semiconductor device such as the width of transfer gates and the dimensions of a contact hole are becoming smaller and smaller. In the reduction of the dimensions, it is difficult to reduce the dimension in the direction of the thickness at the same ratio as the reduction of the dimension in the transverse direction. Therefore, the aspect ratio, which is the ratio of the dimension in the direction of the thickness of the structure of the semiconductor device to the dimension in the direction of the width, has been increased instead. As the semiconductor device becomes more minute and the aspect ratio thereof is increased further, the depth of openings and grooves which must be formed by etching in the manufacturing of the semiconductor device becomes larger than the dimension in the transverse direction.
However, the etching methods available in the prior art are inevitably accompanied by the drawback that the stable formation of openings and grooves having a depth larger than the dimension in the transverse direction is difficult, which will be described hereinafter with reference to the following examples.
Firstly, a process to open a contact hole in a memory cell array portion in a dynamic random access memory chip (referred to as a DRAM chip, hereinafter) is taken as an example. The memory cell array portion and the contact hole are generally formed as shown in
FIGS. 18 through 22
. The following description is in accordance with
FIGS. 18 through 22
.
(a) As shown in
FIG. 18
, after isolation regions
502
are formed on a silicon substrate
501
, transfer gates
504
stacked with an offset silicon oxide film
503
are formed by conventional lithography and etching. Subsequently, a mask pattern is formed by conventional lithography, and n-type impurities are implanted into the silicon substrate
501
by ion implantation. For simplification, the resist pattern at the time of the ion implantation is not illustrated.
(b) As shown in
FIG. 19
, a silicon oxide film is deposited on the whole surface of a wafer by chemical vapor deposition so as to be etched in an anisotropic manner to form side walls
505
.
(c) As shown in
FIG. 20
, mask patterns a re formed by conventional lithography, and n-type impurities and p-type impurities are implanted into the silicon substrate
501
by ion implantation. For simplification, the resist patterns at the time of the ion implantation are not illustrated.
(d) As shown in
FIG. 21
, after a silicon oxide film
506
is deposited, a thick silicon nitride film
507
, which functions as a stopper, is deposited. Subsequently, a silicon oxide film
508
is deposited so as to be planarized by chemical mechanical polishing.
(e) As shown in
FIG. 22
, a contact hole pattern
509
for opening a contact hole
510
on the silicon substrate
501
is formed by conventional lithography. Then, after the silicon oxide film
508
is etched using the silicon nitride film
507
as a stopper, the contact hole
510
is opened on the silicon substrate
501
by etching the silicon nitride film
507
and the silicon oxide film
506
.
In the above-described process, the width of the side walls is set in such a way that the transfer gates of a peripheral circuit portion operate as desired. Here, a problem arises: as side walls with approximately the same width as those of the peripheral circuit portion are also formed in the memory cell array portion, the silicon nitride film deposits and buries most of the spaces between the transfer gates if the width of the silicon nitride film is set in such a way that the function thereof as a stopper is given priority, which causes the etching process of the silicon oxide film to be halted before the completion thereof. On the other hand, if priority is given to the complete etching of the silicon oxide film on the silicon nitride film so that the silicon nitride film is thinned, the function thereof as a stopper is depressed, resulting in short circuiting of the contact hole with the transfer gates.
Next, a process to open a metal wiring contact hole in a DRAM chip and a logic device is given as an example. In this process, a contact hole is formed by etching a silicon oxide film using a silicon nitride film as a stopper, which must be accompanied by high selectivity of silicon oxide for silicon nitride on the bottom of the deep contact hole. However, as is reported in “Characterization of Highly Selective SiO
2
/Si
3
N
4
Etching of High-Aspect-Ratio Holes” (Hisataka Hayashi, Kazuaki Kurihara and Makoto Sekine, Proceedings of Symposium on Dry Process, p. 225-230, 1995), under conditions of C
4
F
8
/CO where high selectivity of silicon oxide for silicon nitride is ensured, a problem arises in that the etching rate is significantly lowered when the etching depth is increased, particularly in a fine contact hole. On the other hand, under conditions of C
4
F
8
/CO/O
2
where the etching rate is not lowered even in the fine contact hole, a problem arises in that sufficient selectivity of silicon oxide for silicon nitride can not be ensured. In other words, under the conditions of high selectivity, an opening can not be easily formed, yet under the conditions where a deep contact hole can be etched, wiring readily causes short circuiting because the silicon nitride film does not function as a stopper, thereby preventing stable opening of the contact hole.
In view of the above-described problems of the conventional techniques, the present invention provides a technique for etching a silicon oxide film using a silicon nitride film as a stopper so that a contact hole is opened in a self-aligned manner, etc., which corresponds to a semiconductor with a microstructure and a high aspect ratio.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, the present invention provides a method of manufacturing a semiconductor device including an etching process for etching a silicon oxide film using a silicon nitride film as a stopper, wherein atoms of one or more kinds selected from a group consisting of carbon and atoms whose reactivity to fluorine and oxygen is equivalent to that of carbon are implanted into said silicon nitride film by an ion implantation method before said etching process, so that selectivity of silicon oxide for silicon nitride in said etching process is increased.
The atoms whose reactivity to fluorine and oxygen is equivalent to that of carbon may include atoms selected from a group consisting of boron, phosphorus, arsenic, and antimony.
It is preferable that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted under the condition that the implantation dose of said atoms, which go beyond said silicon nitride film and reach a portion situated below said silicon nitride film, must be below the level at which the characteristics of that portion are affected.
More specifically, it is preferable that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted not only after a silicon oxide film has been deposited on the silicon nitride film for planarization, but after the silicon oxide film has been etched with sufficiently high selectivity of silicon oxide for silicon nitride until the silicon nitride film on transfer gates has been exposed, that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted after an organic film is formed on said silicon nitride film, and/or that the implantation of said atoms of one or more kinds into said silicon nitride film is conducted when a wafer having said silicon nitride film is inclined at a wider angle than the apparent
Burdett James R.
Daebeler Paul F.
Oki Electric Industry Co. Ltd.
Umez-Eronini Lynette T.
Utech Benjamin L.
LandOfFree
Method of manufacturing of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2827045