Vector data bypass mechanism for vector computer

Details Vector data bypass mechanism for vector computer Vector data bypass mechanism for vector computer

1995-09-01

1998-09-01

Bowler, Alyssa H.

39580004, 39580006, 39580007, G06F 940, G06F 1516

Patent

active

058023844

ABSTRACT:
A bypass mechanism in a vector computer is disclosed. The vector register bypasses data to be written in the inner registers from input or output of the write data register. The bypass mechanism is mainly realized by a selector and a decoder. The selector selects any one of data to be written in the registers at the timing before 2 cycles, data to be written in the registers at the timing before 1 cycle, and the read data from the registers. The decoder controls the selector according to a mask signal from the mask register; a signal of a timing which is before one cycle of the mask signal, and a bypass signal from said controller.

REFERENCES:
patent: 4761754 (1988-08-01), Kinoshita
patent: 4837730 (1989-06-01), Cook et al.
patent: 4888679 (1989-12-01), Fossum et al.
patent: 5019969 (1991-05-01), Izumisawa et al.
patent: 5151995 (1992-09-01), Garcia
patent: 5333281 (1994-07-01), Nishikawa et al.
patent: 5555384 (1996-09-01), Roberts et al.
patent: 5590365 (1996-12-01), Ide et al.
Okamoto et al., "A 200-MFLOPS 100-MHZ 64-BiCMOS Vector-Pipelined Processor (VPP) ULSI" IEEE Journal of Solid-State Circuits, vol. 26, No. 12 1885-1893, (1991).

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