Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
2000-08-16
2002-01-15
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
C327S544000, C327S291000, C327S382000, C307S038000
Reexamination Certificate
active
06339359
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit apparatus in which the operation of circuits when not used is appropriately stopped to reduce the adverse influence of noise.
2. Description of Related Art
FIG. 24
is a diagram showing the configuration of a microcomputer representing a conventional integrated circuit apparatus. In
FIG. 24
,
1
indicates an external electric power supply source, and
2
indicates a microcomputer representing a conventional integrated circuit apparatus.
3
indicates an electric power supply terminal (hereinafter, called a Vcc terminal) for electrically connecting the microcomputer
2
with the external electric power supply source
1
.
4
indicates a ground (GND) level supply terminal (hereinafter, called a Vss terminal) for electrically connecting the microcomputer
2
with an external ground electric level (hereinafter, called a GND level).
16
indicates a control circuit such as a central processing unit (CPU) or a bus interface unit (BIU) or an interrupt control circuit (hereinafter, called a control circuit) such as an interface control unit (ICU) or a direct memory access controller (DMAC).
17
indicates a pre-decoder (or a decoder) for decoding an address of a to-be-controlled circuit output from the control circuit
16
, setting a pre-decode signal to an active state to indicate that the to-be-controlled circuit is controlled by the control circuit
16
, setting each of pre-decode signals of circuits other than the to-be-controlled circuit to an inactive state and outputting the pre-decode signals to a plurality of supply lines of the pre-decode signals.
18
indicates a memory circuit (hereinafter, called a memory) such as a read only memory (ROM), a random access memory (RAM) or a flash memory.
19
indicates a periphery function circuit (hereinafter, called a peripheral circuit).
20
indicates a clock generator for outputting an operation clock signal to each circuit. Each of reference numerals
6
to
15
indicates a buffer circuit (hereinafter, called a port circuit) for a port, a port latch or an input/output drive. Each of reference numerals
21
to
30
indicates a capacitor built-in the microcomputer
2
. Solid lines and solid arrows indicate supply lines of the operation clock signals, and the supply lines are arranged so as to surround the circuits
16
to
20
. Dotted lines and dotted arrows indicate the supply lines of the pre-decode signals arranged so as to surround the circuits
16
to
20
. Also, though a data bus, an address bus and a control bus are arranged so as to surround the circuits
16
to
20
, the data bus, the address bus and the control bus are omitted in FIG.
24
and other drawings to simplify the description of the microcomputer
2
. Thick solid lines indicate power supply lines through which the electric power of the external electric power supply source
1
is supplied to each circuit. The thick dotted lines indicate GND level supply lines through which each circuit is set to the GND level.
Also, because the circuits
16
to
19
are arranged in an area surrounded by the supply lines of the operation clock signals, the supply lines of the pre-decode signals and the above buses, the circuits
16
to
19
are called internal circuits. The port circuits
6
,
7
,
14
and
15
are called left-side port circuits because the port circuits
6
,
7
,
14
and
15
are placed on the left side of the microcomputer
2
. The port circuits
8
and
9
are called upper-side port circuits because the port circuits
8
and
9
are placed on the upper side of the microcomputer
2
. The port circuits
10
and
11
are called right-side port circuits because the port circuits
10
and
11
are placed on the right side of the microcomputer
2
. The port circuits
12
and
13
are called lower-side port circuits because the port circuits
12
and
13
are placed on the lower side of the microcomputer
2
.
In cases where the circuits of the microcomputer
2
are replaced with equivalent circuits of the microcomputer
2
, the connection between the group of internal circuits
16
to
19
and the group of power supply lines is intentionally designed to supply the electric power to the internal circuits
16
to
19
through equivalent resistances, equivalent inductances and equivalent capacitances parasitically existing in the power supply lines, the port circuits
6
to
15
, the capacitors
21
to
30
and other circuits. This design is performed by considering noise generated in the microcomputer
2
according to electromagnetic interference and electromagnetic smog (EMI/EMS). Because of the above design of the power supply lines, an LC filter effect can be obtained in the power supply lines extending from the Vcc terminal
3
to the internal circuits
16
to
19
through the port circuits
6
to
15
. Therefore, the inputting of external noise from the Vcc terminal
3
to the microcomputer
2
and the outputting of internal noise generated in the internal circuits
16
to
19
to the outside of the microcomputer
2
through the Vcc terminal
3
can be prevented.
The LC filter effect in the power supply lines extending from the Vcc terminal
3
to the internal circuits
16
to
19
through the port circuits
6
to
15
is described in detail with reference to FIG.
25
and FIG.
26
A and FIG.
26
B.
FIG. 25
shows an equivalent circuit of the microcomputer
2
shown in FIG.
24
. In
FIG. 25
, reference numerals
32
to
41
indicate a plurality of function blocks arranged in the port circuits
6
to
15
, and the function blocks
32
to
41
are simultaneously operated when one operation clock signal and/or an electric power are supplied to the function blocks
32
to
41
. Also, a specific circuit element required to make each of the port circuits
6
to
15
have a function of the port circuit is arranged in the function block of the port circuit. Reference numerals
42
to
51
indicate equivalent inductances parasitically existing in the power supply lines of the port circuits
6
to
15
, and reference numerals
52
to
61
indicate equivalent capacitances parasitically existing in the power supply lines of the port circuits
6
to
15
. The same constituent elements as those shown in
FIG. 24
are indicated by the same reference numerals as those indicating the constituent elements in
FIG. 24
, and the description of the same constituent elements as those shown in
FIG. 24
is omitted.
A general cause of electric power source noise generated in the microcomputer
2
shown in
FIG. 25
is described.
FIG. 26A
is an explanatory diagram showing a signal transmitting through an inverter circuit in cases where an operation frequency of the inverter circuit is sufficiently low, and
FIG. 26B
is an explanatory diagram showing a signal transmitting through an inverter circuit in cases where an operation frequency of the inverter circuit is high. In
FIG. 26B
, a reference numeral L
1
indicates a parasitic inductance of the power supply line, a reference numeral L
2
indicates a parasitic inductance of the GND supply line, a reference numeral L
3
indicates a parasitic inductance of a signal line, a reference numeral C
1
indicates a parasitic capacitance in an area between the electric power source and the GND level supply source, and a reference numeral C
2
indicates a parasitic capacitance in an area between the signal line and the GND level supply source.
As shown in
FIG. 26A
, in cases where an operation frequency of the inverter circuit is sufficiently low, a level of a signal input to the inverter circuit is sharply changed. In cases where the change of the input signal is sharp, a level of an output signal is not made uncertain, no penetration current flows, so that no electric power source noise occurs.
In contrast, as shown in
FIG. 26B
, in cases where an operation frequency of the inverter circuit is high, the parasitic inductance L
3
of the signal line and the parasitic capacitance C
2
in the area between the signal line and the GND level supply
Cunningham Terry D.
Mitsubishi Denki & Kabushiki Kaisha
Tra Quan
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