Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1999-11-16
2002-04-02
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S057000, C257S347000, C257S350000, C349S042000, C349S044000, C349S046000
Reexamination Certificate
active
06365917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter referred to as TFT) and to a semiconductor device having a circuit structured with a thin film transistor. The present invention relates to such semiconductor devices as electro-optical devices, typically active matrix liquid crystal display devices (hereinafter referred to as AM-LCDs), and semiconductor circuits including processors, etc. The present invention also relates to electronic equipment loaded with the electro-optical devices or semiconductor circuits. Note that throughout this specification semiconductor device indicates general devices that acquire their function through the use of semiconductor characteristics, and that electro-optical devices, semiconductor circuits, and electronic equipment are semiconductor devices.
2. Description of the Related Art
Active matrix type liquid crystal display devices composed of TFT circuits that use polysilicon films have been in the spotlight in recent years. They are the backbone for realizing high definition image displays, in which a multiple number of pixels are arranged in a matrix state, and the electric fields that occur in liquid crystals are controlled in that matrix state.
With this type of active matrix type liquid crystal display device, as the resolution becomes high definition in XGA and SXGA, the number of pixels alone exceeds one million. A driver circuit that drives all of the pixels is therefore extremely complex, and furthermore is formed from a large number of TFTs.
The required specifications for actual liquid crystal display device (also called liquid crystal panels) are strict, and in order for all of the pixels to operate normally, high reliability must be secured for o both the pixels and the driver circuit. If an abnormality occurs in the driver circuit, especially, this invites a fault called a line defect in which one column (or one row) of pixels turns off completely.
However, from a reliability point of view, TFTs that use polysilicon films still fall behind MOSFETs (transistors formed on a single crystal semiconductor substrate), etc., used in LSIs. As long as this shortcoming is not overcome, the point of view that it is difficult to use TFTs when forming an LSI circuit will get stronger.
The applicant of the present invention considers that when comparing a TFT with a MOSFET, the problems associated with the TFT structure affect its reliability (especially hot carrier resistance).
SUMMARY OF THE INVENTION
The present invention is technology for overcoming those problems, and therefore an object of the present invention is to realize a TFT that shows the same or higher reliability than a MOSFET. In addition, another object of the present invention is to realize a high reliability semiconductor device that includes semiconductor circuits formed by circuits using such TFT.
In order to solve the above problems, an n-channel TFT (hereinafter referred to as NTFT) of the present invention has: an n-type first impurity region that functions as a source region or drain region in a semiconductor layer where an inversion layer is formed; and two types of impurity regions (a second impurity region and a third impurity region), in between a channel forming region and the first impurity region, that show the same conductivity type as the first impurity region. The concentration of the impurity that determines the conductivity in the second and third impurity regions is less than that of the first impurity region. The second and third impurity regions function as high resistance regions, also called LDD regions.
The second impurity region is a low concentration impurity region that overlaps a gate electrode with a gate insulating film interposed therebetween, and has the effect of enhancing hot carrier resistance. On the other hand, the third impurity region is a low impurity region that does not overlap the gate electrode, and has the effect to prevent the off current from increasing.
The most important characteristic of the present invention, then, is that a first NTFT and a second NTFT exist on the same substrate, but have different second impurity region lengths, respectively. In other words, according to difference of the operating voltages, the appropriate TFTs having suitable second impurity region length should be arranged. Specifically, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.
Conventionally, it is known that hot carrier resistance increases with a so-called GOLD structure (gate-drain overlapped LDD). This technique has begun to be applied to TFTs, but the problem that with a conventional GOLD structure the off current increases (the current flow when the TFT is in an off state) has been unreasonably ignored.
The applicant of the present invention considers that the above problem must be resolved, and investigates to verify that the off current is reduced dramatically by forming an impurity region (the third impurity region) that does not overlap the gate electrode. Therefore it can be said that the present invention is characterized in the active formation of the third impurity region.
Note that the gate electrode is an electrode that intersects with the semiconductor layer with a gate insulating film interposed therebetween, and is an electrode for applying an electric field to the semiconductor layer and forming an inversion layer. The portion of a gate wiring that intersects with the semiconductor layer with a gate insulating film interposed therebetween is the gate electrode.
In addition, the film thickness of the gate electrode of the present invention decreases either linearly or stepwise from a central flat section, at the periphery of the gate electrode, outward. Namely, it is characterized by being patterned into a tapered shape.
The second impurity region is doped through (passing an impurity through) the tapered region of the gate electrode with the impurity to impart conductivity. Therefore the concentration gradient reflects the inclination (change in film thickness of the tapered portion) of the side face of the gate electrode. In other words, the concentration of the impurity doped into the second impurity region increases gradually from the channel forming region to the first impurity region.
This is caused by the change in the depth that the impurity reaches due to the difference in film thickness in the tapered region. In other words, when looking at the impurity concentration distribution in the depth direction, the depth at which the doped impurity is at peak concentration changes along with the inclination of the tapered portion of the gate electrode.
An impurity concentration gradient can be formed in the inside of the second impurity region with this type of structure. The present invention is characterized by actively forming this type of such a concentration gradient, forming a TFT structure that enhances the electric field relaxation effect.
Further, the structure of other gate electrodes in the present invention is a laminate of a first gate electrode, in contact with the gate insulating film, and a second gate electrode formed on the first gate electrode. Of course, a single layer first gate electrode may also be used.
In this structure, the side face (tapered portion) of the first gate electrode is has a tapered shape that forms with the gate insulating film an angle (shown by &thgr;, and hereinafter referred to as taper angle) equal to or greater than 3° and equal to or less than 40° (desirable if equal to or greater than 5° and equal to or less than 35°, even better if equal to or greater than 8° and equal to or less than 20°). On the other hand, the width of the second gate electrode in the longitudinal direction of the channel is narrower than the first gate electrode.
Also for a thin film transistor having the above type of laminated gate electrode, the concentration distribution of the impurity
Flynn Nathan
Forde Remmon R.
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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