Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2000-09-18
2002-07-23
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S322000
Reexamination Certificate
active
06423959
ABSTRACT:
This application is based on Japanese Patent Application HEI 11-287337 filed on Oct. 7, 1999, all the content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image pickup device, a method of controlling the same, a solid-state image pickup apparatus such as a still camera including a monitor screen, and a method of controlling the same.
In this specification, one transfer stage is defined as a minimum unit of an electric charge transfer region to which electric charge is transferred when a plurality of pulse signals having different phases are applied to charge transfer electrodes successively disposed on a charge transfer path.
For example, when charge in the charge transfer path is driven by signals having four phases, four pulse signals having mutually different phases are respectively applied to four charge transfer electrodes successively arranged on the charge transfer path. In this operation, a region to which electric charge is transferred is referred to as one transfer stage. For example, in the four-phase driving, a region in which four charge transfer electrodes are disposed is called one transfer stage.
In an n-phase driving operation (n is an integer equal to or more than two), a region in which n successive charge transfer electrodes are arranged is referred to as one transfer stage.
2. Description of the Related Art
FIG. 41
shows in a plan view a general configuration of a solid-state image. pickup device.
A solid-state image pickup device X of
FIG. 41
includes a semiconductor substrate
101
, a plurality of photoelectric converter elements
103
arranged in a row direction and in a column direction on a two-dimensional plane of a surface of the substrate
101
, a plurality of vertical charge transfer paths
105
for reading out signal charge accumulated in the photoelectric converter elements
103
and for sequentially transferring the charge in the column direction, a horizontal charge transfer path
107
connected to an end section of each of the vertical charge transfer paths
105
for transferring in a horizontal direction the charge transferred from the vertical charge transfer paths
105
, and an output amplifier
111
for amplifying the charge transferred from the horizontal charge transfer path
105
and for outputting charge resultant from the amplification to an external device.
The device X further includes a readout gate
103
a
between the photoelectric converter
103
and the vertical charge transfer path
105
to read charge from the converter
103
to the path
105
.
FIG. 42
shows a cross-sectional view of the horizontal charge transfer path
107
.
The path
107
includes a p-type well layer
108
formed in the semiconductor substrate
101
, an n-type conductor layer
118
manufactured in the layer
108
, and two layers of polycrystalline silicon including a first polycrystalline silicon layer and a second polycrystalline silicon layer fabricated on the substrate
101
.
The n-type conductor layer
118
includes a region
118
a
having a low concentration of n-type impurity and a region
118
b
having a high concentration of n-type impurity in an alternate fashion. The low-concentration region
118
a
forms a potential barrier B having high potential energy and the high-concentration region
118
b
constitutes a potential well W having low potential energy.
The potential barrier and the potential well are alternately disposed in a horizontal direction. One set including one of the potential barriers and one of the potential wells forms one charge transfer unit (to be referred to as one packet herebelow). A large number of packets are manufactured in the horizontal direction.
On the low-concentration region
118
a
, polycrystalline silicon electrodes (horizontal transfer electrodes
121
-
0
,
121
-
2
,
121
-
4
, etc.) are fabricated in a first layer, and polycrystalline silicon electrodes (horizontal transfer electrodes
121
-
1
,
121
-
3
,
121
-
5
, etc.) are formed in a second layer.
The electrode
121
-
0
is connected to the electrode
121
-
1
, and a voltage waveform &phgr;
1
is applied thereto. The electrode
121
-
2
is connected to the electrode
121
-
3
, and a voltage waveform &phgr;
2
is applied thereto. Similarly, the electrode
121
-
4
is connected to the electrode
121
-
5
, and a voltage waveform &phgr;
1
is applied thereto.
FIG. 43
is a plan view primarily showing a layout of the vertical charge transfer electrodes.
This layout includes four vertical charge transfer electrodes EV, i.e., EV
1
to EV
4
in a vertical direction for first one of the photoelectric converters
103
arranged in a column direction. For each of second and third ones of the converters
103
sandwiching the first one converter
103
therebetween, four vertical charge transfer electrodes E
5
to E
8
are disposed.
For the vertical charge transfer electrodes EV
1
to EV
8
, there are further included a driving circuit, not shown, to apply voltage waveforms V
1
to V
8
to the respective vertical charge transfer electrodes EV
1
to EV
8
.
The voltage waveforms V
1
to V
4
(or, V
5
to V
8
) are controlled, for example, as follows. To form a potential barrier B in the vertical charge transfer path
105
, 0 V is applied to the vertical charge transfer electrodes; to form a potential well W in the vertical charge transfer path
105
, 8 V are applied thereto; and to read electric charge from the photoelectric converter
103
, 15 V are applied thereto.
The vertical charge transfer path
105
is electrically linked with a region of the horizontal charge transfer path
107
in which one potential well W is formed for each packet.
Referring now to
FIGS. 43
,
44
A to
44
C, and
45
A to
45
C, description will be given of operation of the solid-state image pickup device X.
Assume that the vertical charge transfer electrodes are first set as EV
1
=0 V, EV
2
=8 V, EV
3
=8 V, and EV
4
=0 V to thereafter set the electrode V
3
to 15 V.
As shown in
FIG. 44A
, charge accumulated in the photoelectric converters
103
is read therefrom via the transfer gate
103
a
to the vertical charge transfer path
105
. The electrode E
3
is then restored to 8 V.
As can be seen from
FIG. 44B
, all charge read out to the transfer path
105
is transferred one transfer stage in the vertical direction to the horizontal charge transfer path
107
.
Description will now be given in detail of the operation to transfer charge through the vertical charge transfer path
105
in a step of one transfer stage, i.e., in a stage-by-stage way.
The vertical charge transfer electrode EV
4
is set to 8 V. Charge is distributed to regions below the vertical charge transfer electrodes EV
2
to EV
4
.
Thereafter, the transfer electrode EV
2
is set to 0 V. Charge is confined in a semiconductor region below the transfer electrodes EV
3
and EV
4
.
When the transfer electrode EV
5
(EV
1
) is set to 8 V, charge is dispersed in a semiconductor region below the transfer electrodes EV
3
to EV
5
.
When the transfer electrode EV
3
is set to 0 V, charge is confined in a semiconductor region below the electrodes EV
4
and EV
5
.
When the electrodes EV
6
(EV
2
) and EV
4
(EV
8
) are respectively set to 8 V and 0 V, charge is accumulated in a semiconductor region below the electrodes EV
5
and EV
6
.
Charge read from one photoelectric converter
103
to the transfer stage
41
of the vertical charge transfer path
105
contiguous to the horizontal charge transfer path
107
in the vertical direction is fed to the transfer path
107
.
As shown in
FIG. 44C
, the charge fed to the transfer path
107
is then transferred through the path
107
and is outputted to an external device.
The operation above is thereafter conducted such that the charge read out to the vertical charge transfer path
105
is again transferred one transfer stage
141
in the vertical direction to the horizontal charge transfer path
107
.
The electric charge read out to the transfer stage
141
of the v
Ikeda Katsumi
Masukane Kazuyuki
LandOfFree
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