Digital speed control system

Details Digital speed control system Digital speed control system

1976-07-08

1978-01-03

Thesz, Joseph M.

Registers

Platform operated

Platform actuated traffic counters

180105E, 235 92CC, 235 92TC, 235 92R, G06M 302, G06M 308, B60K 3100

Patent

active

040668762

ABSTRACT:
A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register. The inputs of the Acceleration Register are coupled to the outputs of the Actual Count Register so that during the transfer signal the complement of the first binary number is loaded into the Acceleration Register. A decoder connected to the outputs of the Error Register interprets its contents, and a second decoder interprets the contents of the Acceleration Register.

REFERENCES:
patent: 3064889 (1962-11-01), Hupp
patent: 3885137 (1975-05-01), Ooya et al.
patent: 3891046 (1975-06-01), Oicles

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