Nonvolatile semiconductor memory device having an array...

Details Nonvolatile semiconductor memory device having an array... Nonvolatile semiconductor memory device having an array...

2000-01-19

2002-04-30

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Diode arrays

C365S185110, C365S185030, C365S185170, C365S185180, C365S230030

Reexamination Certificate

active

06380636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a structure of a nonvolatile memory cell array suitable to high-density integration.
2. Description of the Background Art
FIG. 2
schematically shows a structure of a memory cell array in a conventional nonvolatile semiconductor memory device. In
FIG. 27
, the memory cell array includes a plurality of nonvolatile memory cells MC arranged in rows and columns.
FIG. 27
shows representatively nonvolatile memory cells MC
11
, MC
12
, MC
21
and MC
22
arranged in two rows and two columns. A predetermined number of memory cells among the memory cells arranged in a column are coupled to a sub-bit line SBL. In
FIG. 27
, memory cells MC
11
and MC
21
are connected to a sub-bit line SBL
1
, and memory cells MC
12
and MC
22
are connected to a sub-bit line SBL
2
.
A word line WL is arranged for the memory cells arranged in a row. In
FIG. 27
, memory cells MC
11
and MC
12
are connected to a word line WL
1
, and memory cells MC
21
and MC
22
are connected to a word line WL
2
.
A plurality of sub-bit lines arranged extending in the column direction and aligned in the same column. A sub-source line SSL
1
commonly connecting the sources of memory cells MC
11
, MC
21
, . . . is provided corresponding to sub-bit line SBL
1
. Likewise, a sub-source line SSL
2
commonly connecting the sources of memory cells
12
, MC
22
, . . . is provided corresponding to sub-bit line SBL
2
. Sub-source lines SSL
1
and SSL
2
are connected to a source line SL via source-side block select transistors SGS
1
and SGS
2
receiving on their gates a source-side block select signal SS. Sub-bit lines SBL
1
and SBL
2
are connected respectively to main bit lines MBL
1
and MBL
2
via drain-side block select transistors SGD
1
and SGD
2
receiving on their gates a drain-side block select signal SD.
Main bit lines MBL
1
and MBL
2
each are arranged corresponding to a memory cell column and are connected to a plurality of sub-bit lines via the block select transistors receiving a drain-side block select signal. Brief description will now be given on operations of the nonvolatile semiconductor memory device shown in FIG.
27
.
Referring first to
FIG. 28
, an operation for writing data into memory cell MC
11
will be described. In this case, drain-side block select signal SD is set to H-level, and drain-side block select transistors SGD
1
and SGD
2
are set to the on state. Further, source-side block select signal SS is set to L-level, and source-side block select transistors SGS
1
and SGS
2
are set to the off state so that sub-bit lines SSL
1
and SSL
2
are electrically floated. Word line WL
1
is supplied with a programming high voltage Vhh. Unselected word line WL
2
maintains L-level. Main bit line MBL
1
is supplied with a voltage at the ground voltage level of L-level. Main bit line MBL
2
is supplied with a program inhibiting voltage Vh (<Vhh).
In memory cell MC
11
, the drain is connected to sub-bit line SBL
1
, and is set to the ground voltage level, the source thereof is connected to sub-source line SSL
1
, and electrically floated, and the control gate is connected to word line WL
1
, and receives programming high voltage Vhh. In this state, memory cell MC
11
is in such a state that a Fowler-Nordheim tunneling current (F-N tunneling current) flows from a drain region to a floating gate, and electrons are accumulated in the floating gate so that the threshold voltage rises. This state in which threshold voltage Vth is raised is called a “programmed state”.
In memory cell MC
12
, the drain receives program inhibiting voltage Vh transmitted onto sub-bit line SBL
2
. In this state, memory cell MC
12
is in such a state that a voltage difference (Vhh−Vh) between the drain and the control gate is low, and F-N tunneling current does not flow so that electrons are not injected into the floating gate, and programming of data into memory cell MC is not performed.
This state wherein the programming is not performed corresponds to a state wherein the threshold voltage Vth is low.
Now, a data read operation will now be described with reference to FIG.
29
. In the following description, it is assumed that stored information is read out from memory cells MC
11
and MC
12
, which are in the programmed state (high threshold voltage state (Hi-Vth state)) and the non-programmed state (low threshold voltage state (Low-Vth state)), respectively. In this case, drain-side block select signal SD is set to H-level, and drain-side block select transistors SGD
1
and SGD
2
are turned on so that sub-bit lines SBL
1
and SBL
2
are electrically connected to main bit lines MBL
1
and MBL
2
, respectively. The source-side block select signal SS is set to H-level, and source-side select transistors SGS
1
and SGS
2
are turned on so that sub-source lines SSL
1
and SSL
2
are connected to source line SL. Source line SL is set to ground voltage GND level.
Word line WL
1
is supplied with a read voltage Vr intermediate the high and low threshold voltages Hi-Vth and Low-Vth. Main bit lines MBL
1
and MBL
2
are supplied with a precharge voltage Vp, and sub-bit lines SBL
1
and SBL
2
are precharged to precharge voltage Vp level via drain-side block select transistors SGD
1
and SGD
2
.
Since memory cell MC
11
is in the high threshold voltage state, and has the threshold voltage higher than read voltage Vr, memory cell MC
11
maintains the off state, and sub-bit line SBL
1
maintains the voltage level of precharge voltage Vp. Memory cell MC
12
is in the low threshold voltage state, and is turned on in accordance with read voltage Vr on word line WL
1
so that a current flows from sub-bit line SBL
2
via sub-source line SSL
2
and source-side block select transistor SGS
2
to source line SL at the ground voltage GND level, and the voltage level on sub-bit line SBL
2
lowers.
Main bit lines MBL
1
and MBL
2
are provided with sense amplifier circuits, which in turn sense the changes in voltage level of precharge voltage Vp on main bit lines MBL
1
and MBL
2
(whether a current flows or not) for reading the data of memory cells. The output data of the sense amplifier circuits provided for main bit lines MBL
1
and MBL
2
is selected according to a column address signal depending on the output bit width of the nonvolatile semiconductor memory device, and the external reading of the memory cell data is performed.
In the foregoing nonvolatile semiconductor memory device, the memory cell of one bit is formed of one transistor (stacked gate type MOS (insulated gate type field effect) transistor) so that an area occupied by one bit of the memory cell can be small, and the memory cell structure is suitable to high-density integrationization.
FIG. 30
schematically shows a planar layout of the memory cell array shown in FIG.
27
. In
FIG. 30
, N-type impurity diffusion layers
1
-
1
and
1
-
2
forming sub-source lines SBL
1
and SBL
2
are arranged in the column direction. N-type impurity diffusion layers
2
-
1
and
2
-
2
extending in the column direction and forming sub-source lines SSL
1
and SSL
2
are arranged alternately with impurity diffusion layers
1
-
1
and
1
-
2
. Impurity diffusion layers
1
-
1
and
1
-
2
are coupled to impurity regions of drain-side block select transistors SGD
1
and SGD
2
shown in FIG.
27
. Likewise, impurity diffusion layers
2
-
1
and
2
-
2
are coupled to impurity regions of source-side block select transistors SGS
1
and SGS
2
shown in FIG.
27
.
Conductive layers
3
-
0
-
3
-n which form word lines WL
1
-WLn, respectively, are arranged in the direction perpendicular to impurity diffusion layers
1
-
1
,
1
-
2
,
2
-
1
and
2
-
2
. These conductive layers
3
-
0
-
3
-n are formed of, e.g., a second level polycrystalline silicon layer.
A low resistance conductive layer
4
extending in the row direction for transmitting drain-side block select signal SG is arranged crossing drain-side block select transistors SGD
1
and SGD
2
.

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