Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-06-05
2002-04-23
Banks, Derris H. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S288000
Reexamination Certificate
active
06375550
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a method of fabricating a semiconductor wafer, and more particularly to a method and apparatus for enhancing uniformity during polishing of a semiconductor wafer.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on a surface of a wafer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface to a subsequent processing step. For example, an insulator layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface thereof.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes a wafer carrier or holder and a platen such as a polishing table or moving polishing belt, between which the semiconductor wafer is positioned. The wafer carrier and the platen are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical-mechanical planarization or chemical-mechanical polishing (CMP). The chemical slurry is generally an aqueous acidic or basic solution having a number of abrasive particles, such as silica (SiO
2
), alumina (Al
2
O
3
), or ceria (Ce
2
O
3
) particles, suspended therein.
Polishing pressure, that is the pressure applied on a wafer by the wafer carrier or a polishing pad secured to the polishing platen, is generally maintained at a constant (e.g. uniform) level across the entire surface area of the wafer. Such a uniform polishing pressure is maintained in an effort to ensure that the same amount of wafer material is removed from all of the sections of the surface of the wafer. Generally speaking, the amount of material removed from the surface of the wafer is proportional to the product of the polishing pressure and the relative velocity of the wafer. It should be appreciated that the relative velocity of the wafer is generally a function of the rotation of the wafer by the wafer carrier.
Heretofore polishing systems have utilized a number of techniques to maintain a uniform polishing pressure. For example, an air bladder has been utilized below the polishing pad of the polishing platen. Inflation of the air bladder serves to apply a uniform pressure to the back of the polishing pad and hence the wafer being polished thereon. Moreover, polishing systems have heretofore been designed to include a number of independently controlled air bladders which can be independently inflated and deflated in order to selectively increase or decrease pressure exerted on the polishing pad.
However, such heretofore designed polishing systems have a number of drawbacks associated therewith. For example, it is known that during manufacture of certain wafer designs, non-uniformity is created in areas of the wafer which are different than the areas of the wafer in which non-uniformity is created in other wafer designs. In other words, it is desirable to adjust the polishing pressure in different locations for certain wafer designs relative to the locations in which polishing pressure is adjusted for other wafer designs. However, existing polishing system designs do not allow for such flexibility. In particular, the location of the air bladders in heretofore designed polishing systems is fixed. Hence, if a certain wafer design requires an increase or decrease in polishing pressure at a location of the wafer which does not correspond to the location of the air bladders of the polishing platen, a separate, dedicated polishing platen must be procured. This is a relatively expensive notion and often requires significant amounts of labor to swap out the polishing platens.
What is needed therefore is a method and apparatus for polishing a semiconductor wafer which overcomes the above-mentioned drawbacks. What is also need is a method and apparatus for polishing which provides for selective increases and decreases in polishing pressure without requiring the use of multiple polishing platens.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided a method of operating a chemical-mechanical polishing system which has a wafer carrier assembly which includes a carrier body. The method includes the step of securing a first fixture to the carrier body. The first fixture is configured to apply pressure to a first semiconductor wafer at a first number of predetermined locations. The method also includes the step of polishing the first semiconductor wafer while the first fixture is secured to carrier body. The method further includes the step of removing the first fixture from the carrier body. Yet further, the method includes the step of securing a second fixture to the carrier body. The second fixture is configured to apply pressure to a second semiconductor wafer at a second number of predetermined locations which are different than the first number of predetermined locations of the first wafer. Moreover, the method includes the step of polishing the second semiconductor wafer while the second fixture is secured to the carrier body.
Pursuant to another embodiment of the present invention, there is provided a chemical-mechanical polishing apparatus for polishing a first side of a semiconductor wafer. The apparatus includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier assembly having a carrier body. The wafer carrier assembly is adapted to (i) engage the wafer by a second side of the wafer, and (ii) apply pressure to the wafer in order to press the wafer against the polishing surface of the polishing platen. The wafer carrier assembly is operable in a first carrier configuration and a second carrier configuration. A first fixture which is configured to apply pressure to the wafer at a first number of predetermined locations is secured to the carrier body when the wafer carrier assembly is operated in the first carrier configuration. A second fixture which is configured to apply pressure to the wafer at a second number of predetermined locations which are different than the first number of predetermined locations is secured to the carrier body when the wafer carrier assembly is operated in the second carrier configuration.
Pursuant to yet another embodiment of the present invention, there is provided a method of operating a chemical-mechanical polishing system which has a polishing surface associated therewith. The method includes the step of securing a first fixture to a fixture receptacle which is located proximate to the polishing surface. The first fixture is configured to apply pressure to the polishing surface at a first number of predetermined locations. The method also includes the step of polishing a first semiconductor wafer while the first fixture is secured to the fixture receptacle. Moreover, the method includes the step of removing the first fixture from the fixture receptacle. In addition, the method includes the step of securing a second fixture to the fixture receptacle. The second fixture is configured to apply pressure to the polishing surface at a second number of predetermined locations which are different than the first number of predetermined locations. In additi
Banks Derris H.
LSI Logic Corporation
Maginot Addison & Moore
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