Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
1998-09-25
2002-01-29
Zimmerman, Mark (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
C345S422000, C345S426000, C345S589000, C345S592000
Reexamination Certificate
active
06342882
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and method and a transmission medium, and, more specifically, to an image processing apparatus and method and a transmission medium in which one of a plurality of rendering modes is selected and set and a rendering process is executed in accordance with the rendering mode thus set.
In such image processing apparatus as a computer gate machine, an image is prescribed by a combination of a plurality of polygonal regions and the entire object is rendered on a polygon-by-polygon basis. Such image processing apparatuses can display, on a monitor, polygons in a virtual space while changing their states in various manners.
FIG. 1
is a block diagram showing an example configuration of an image processing apparatus of the above kind. In this example, the CPU
11
performs various operations such as a coordinate conversion, a light source calculation, and a vector operation as well as controls the respective sections. A main bus
12
that transfers data at relatively high speed and a sub-bus
13
that transfers data at relatively low speed are connected to the CPU
11
. The CPU
11
can exchange data via the buses
12
and
13
. A CD-ROM drive
14
, which is connected to the sub-bus
13
, can read out any of various data or programs from a CD-ROM as a recording medium that is mounted therein in accordance with an instruction that is sent from the CPU
11
.
A main memory
15
and a GPU (graphic processing unit)
16
are connected to the main bus
12
. The main memory
15
stores data that has been read out from the CD-ROM drive
14
, data as an operation result of the CPU
11
, and other data. The GPU
16
performs a rendering operation while reading out data from the main memory
15
when necessary, and stores processed image data in a VRAM (video random access memory)
17
. Further, the GPU
16
reads out image data from the VRAM
17
and supplies it to a D/A converter
18
. The D/A converter
18
converts image data (digital signal) that is supplied from the GPU
16
into an analog signal and outputs it to a monitor (not shown) as a video signal.
In rendering a blended image by superimposing two images on each other in the above image processing apparatus, if one of the two images has a translucent region, such as a polygonal region, pixel data of the two images are blended together by using alpha data that are added to the image data (color data) of the respective subject images. The alpha data is a coefficient that takes a value in a range of 0.0 to 1.0. A value 1.0 is added to an opaque polygon, and a value 0.0 is added to a transparent polygon. A value in a range of 0.0 to 1.0 is added to a translucent polygon (the degree of transparency increases as the value becomes closer to 0.0, and decreases as the value becomes closer to 1.0).
For example, when a translucent image G is superimposed on an opaque image F, blended pixel data Cb is given by
Cb=As·Cs+
(1−
As
)
Cd
(1)
where a notation is employed that Cd and Ad are pixel data and alpha data of the image F and Cs and As are pixel data and alpha data of the image G.
This type of process is called alpha blending.
FIG. 2
is a block diagram showing a more detailed example configuration of the GPU
16
and the VRAM
17
as circuits for performing alpha blending. In this example, the GPU
16
is composed of an interpolation circuit
21
and an alpha blending circuit
22
and the VRAM
17
has a Z buffer
31
and a frame buffer
32
.
The interpolation circuit
21
performs interpolation on a polygon that has been read out from the main memory
15
(see FIG.
1
), and supplies pixel data Cs of the interpolated polygon to the alpha blending circuit
22
and supplies depth data Zs and alpha data As of the interpolated polygon to the VRAM
17
. The alpha blending circuit
22
generates pixel data Cb by blending pixel data Cd of a polygon that is stored in the VRAM
17
and the pixel data Cs that is supplied from the interpolation circuit
21
by using the alpha data that is supplied from the interpolation circuit
21
. The alpha blending circuit
22
outputs the generated image data Cb to the VRAM
17
.
The Z buffer
31
stores one of depth data Zs that is supplied from the interpolation circuit
21
of the GPU
16
, the one depth data Zs having a larger value (indicating that the image is located closer to the viewer's side). The frame buffer
32
stores image data of an image to be displayed on the monitor. The VRAM
17
stores alpha data As that is supplied from the interpolation circuit
21
in a predetermined area.
FIG. 3
illustrates an example process of rendering a blended image by superimposing two images on each other by using the alpha blending circuit shown in FIG.
2
. In this example, it is assumed that pixel data Cd and alpha data Ad of an image
110
are stored in the VRAM
17
in advance and that an image
120
is to be superimposed on the image
110
. In
FIG. 3
, pixel data of polygons that define each image are shown on the left side and corresponding alpha data values are shown on the right side.
In this example, a polygonal region
112
of the image
110
is opaque and the value of the corresponding alpha data Ad is 1.0. A region
122
of the image
120
is translucent and the value of its alpha data As is 0.5. A region
111
of the image
110
and a region
121
of the image
120
are transparent, and the values of their alpha data Ad and As are 0.0.
The alpha blending circuit
22
generates pixel data Cb by blending the pixel data Cd and Cs of the images
110
and
120
by using the alpha data As of the image
120
(refer to Equation (1)). The generated pixel data Cb and the alpha data As are rendered in (written to) the VRAM
17
as an image
130
. The alpha data of the rendered image is newly denoted by Ad. The value of the pixel data Cb of the image
130
is the same as that of the pixel data Cd of the image
110
in regions
131
and
132
, and is equal to (0.5 Cs+0.5 Cd) in a region
133
.
In this case, although blending is correctly done for the pixel data Cb, the alpha data Ab is rendered as being the same as the alpha data As of the image
120
. Since the opaque region
112
and the translucent region
122
have been superimposed on each other, the value of the alpha data Ab corresponding to the regions
132
and
133
should be 1.0 indicating that those regions are opaque. Therefore, in this case, the rendering operation has not been performed correctly.
Incidentally, a method called an alpha test may be used in an image drawing process of the above kind.
FIG. 4
is a block diagram showing an example configuration of the GPU
16
and the VRAM
17
in which a circuit for performing an alpha test is provided. The components in
FIG. 4
that have corresponding components in
FIG. 2
are given the same reference numerals as in FIG.
2
and descriptions therefor will be omitted where appropriate. In this example, an alpha test circuit
23
is provided between the interpolation circuit
21
and the VRAM
17
. A predetermined constant C is set in the alpha test circuit
23
. The alpha test circuit
23
compares the value of alpha data As that is supplied from the interpolation circuit
21
with the value of the constant C, and judges whether a comparison result satisfies a predetermined condition. In accordance with a judgment result, the alpha test circuit
23
makes a selection as to whether to render blended pixel data Cb that has been generated by the alpha blending circuit
22
and the alpha data As in the VRAM
17
.
FIG. 5
illustrates an example process of rendering a blended image in which the value of the constant C of the alpha test circuit
23
shown in
FIG. 4
is set at 1.0 and the condition is set to “EQUAL.” The parts in
FIG. 5
that have corresponding parts in
FIG. 3
are given the same reference symbols as in FIG.
3
and descriptions therefor will be omitted where appropriate. In this example, the alpha test circuit
23
compares the values of alpha data As of an i
Lerner David Littenberg Krumholz & Mentlik LLP
Santiago Enrique L
Sony Computer Entertainment Inc.
Zimmerman Mark
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