Performance monitoring in multiprocessor system with interrupt m

Details Performance monitoring in multiprocessor system with interrupt m Performance monitoring in multiprocessor system with interrupt m

Filed on

1996-06-26

Date issued

1998-09-01

Examiner

Sheikh, Ayaz R.

Other Related Categories

39518313, G06F 700

Type

Patent

Status

active

Patent number

058023780

Description

ABSTRACT:
The present invention provides a system and method which ensures that machine state data, for each CPU in an MP system, corresponding to a specific point in time will always be saved, regardless of whether the system interrupt handler is enabled or disabled. A series of special purpose registers (SPR) are included, which are associated with the performance monitoring mechanism in each processor in the MP system. A time base mechanism in each CPU is used and synchronized across the entire MP system. When the time base mechanism requests that the machine state be recorded, the performance monitor then immediately stores the machine state values in the special purpose registers. Thus, the state of the each CPU in the MP system is saved at the identical point in time. The performance monitor issues an interrupt request to the interrupt handler and, if interrupts are enabled, the machine state data is stored for post-processing, or the like. However, if the interrupt handler has disabled interrupts, then the machine state data remains in the SPRs until interrupts are enabled and the data (corresponding to the same point in time) is then read from the special purpose registers into memory, or the like, for post-processing.

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