Semiconductor memory device having pairs of bit lines...

Details Semiconductor memory device having pairs of bit lines... Semiconductor memory device having pairs of bit lines...

1998-12-15

2002-03-12

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S369000, C257S903000

Reexamination Certificate

active

06355982

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a pattern layout of a bit line and a power supplying line or a grounded line in a memory cell array, for use in, for example, a SRAM (static random access memory).
FIG. 5
shows a pattern layout of memory cells, bit line pairs, a power supplying line and a grounded line in a memory cell array of a conventional SRAM.
In
FIG. 5
, memory cells MC are arranged in a matrix. A word line WL for selecting a cell is connected in common to the memory cells on the same row. A pair of bit lines BL and /BL for transmitting and receiving cell data are connected in common to the memory cells on the same column. The word line WL and the pair of bit lines BL and /BL are arranged at right angles with each other.
A power supplying line Vdd is connected in common to the memory cells of the same row. A grounded line Vss is connected to the memory cells of the same row. The power supplying line Vdd and the ground line Vss are made of a layer different from that of the bit line pairs BL and /BL and arranged in parallel with the word line WL.
Since the bit line pairs BL and /BL are required to be low in resistance, they are generally made of metal, for example, aluminum.
On the other hand, in the case of a large capacity memory, the power supplying line Vdd and the grounded line Vss are formed of a single-layer wire made of polycrystalline silicon film doped with an impurity, or a multi-layer wire made of a polycrystalline silicon film and a silicide such as WSi or MoSi.
In this case, in order to make the power supplying line Vdd and the grounded line Vss low in resistance, thereby reducing the drop in potential, the aforementioned single layer or the multi-layer wire is generally backed with a metal wire, such as aluminum.
The power supplying line Vdd and the grounded line Vss may be made of metal, such as aluminum, like the bit line pairs BL and /BL. Further, the power supplying line Vdd and the grounded line Vss may make of the same layer as that of the word line WL or another layer.
The pattern layout of the SRAM as described above is advantageous in that the pattern area per memory cell (cell size) can be small, for the reason that the power supplying line Vdd and the grounded line Vss are made of a layer different from that of the bit line pairs BL and /BL.
However, for the same reason, the pattern layout of the aforementioned SRAM is disadvantageous in that a large number of manufacturing processes are required, resulting in an increased manufacturing cost.
Further, if the size of a memory cell is reduced by refinement of elements, the interval between the bit lines BL and /BL connected to the memory cell, i.e., the interval between the bit lines of the adjacent columns, is reduced. As a result, when a signal current flows through the bit lines of a column, the bit lines of the adjacent column may be influenced (a so-called coupling occurs), resulting in a problem such as a malfunction or destruction of data.
As a method for suppressing a coupling noise, Jpn. Pat. KOKAI Appln. No. 61-206254 relating to “Semiconductor Memory Device” discloses a technique for reducing crosstalk (coupling) by arranging the power supplying line Vdd between bit lines BL and /BL of the adjacent columns along the bit lines and a grounded line GND. This technique is shown in FIG.
6
. In
FIG. 6
, a reference symbol MC denotes a memory cell and WL a word line.
Jpn. Pat. KOKAI Appln. No. 4-366494 relating to “Semiconductor Memory Device” discloses a technique for preventing occurrence of a defect in data reading and writing by arranging a power supplying line PL between a digit line DL or /DL and a grounded line GL. This technique is shown in FIG.
7
. In
FIG. 7
, a reference symbol MC denotes a memory cell and WL a word line.
These techniques, however, are disadvantageous in that reduction in pattern area per memory cell is limited, since the bit line pairs BL and /BL (or digit line pairs DL and /DL), the power supplying line Vdd and the grounded line GND (or GL) are made of the same layer.
Thus, the conventional semiconductor devices have a drawback in that reduction in pattern area per memory cell is limited, since the power supplying line and the grounded line are formed in the same layer along the bit lines to reduce the coupling between the adjacent bit lines.
BRIEF SUMMARY OF THE INVENTION
The present invention solves the above drawbacks of the conventional art. An object of the present invention is to provide a semiconductor memory device, which can reduce coupling between the adjacent bit lines and relax the limitation in reduction of the pattern area per memory cell.
According to the present invention, there is provided a semiconductor memory device comprising: a memory cell array in which memory cells of a static type are arranged in a matrix; a plurality of pairs of bit lines extending in a column direction of the memory cell array, each of the pairs of bit lines being connected in common to memory cells on a same column of the memory cell array, and the bit lines of each of the pairs being arranged on both sides of the memory cells on the same column; a plurality of word lines extending in a row direction of the memory cell array and connected in common to memory cells on a same row of the memory cell array; a grounded line, for supplying a ground potential to the memory cells, formed of a layer same as that of the pairs of bit lines and extending in the column direction; and a power supplying line, for supplying a power potential to the memory cells, formed of a layer different from that of the pairs of bit lines.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 4710897 (1987-12-01), Masuoka et al.
patent: 5239201 (1993-08-01), Asano
patent: 6005296 (1999-12-01), Chan
patent: 61-206254 (1986-09-01), None
patent: 4-366494 (1992-12-01), None

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