Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2000-01-27
2002-01-08
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S597000, C438S611000, C438S618000
Reexamination Certificate
active
06337263
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for improving the quality of metal conductor tracks on wafers, in which each metallizing plane, after its deposition and structuring, is covered by an interlevel dielectric (ILD).
Modern semiconductor chips as a rule have a plurality of metal conductor track planes that are each separated from one another by interlevel dielectrics (ILDs) or insulation oxides. Those metal conductor tracks, which are typically formed of AlCu, are made by using conventional photolithography and as a rule have very slight feature widths. In other words, the metal conductor tracks are extremely narrow. Differences in the coefficients of thermal expansion of the various materials can lead to the creation of holes or voids in the metal conductor tracks, especially because of the small feature widths. Often, such voids in the metal (so-called stress voids), which have a considerable influence on the function or reliability of the semiconductor chip, are not detectable by evaluating layer resistances or on the basis of yields.
However, the greatly increased stress migration is a considerable threat to reliability and quality.
In order to overcome or at least ameliorate that problem, after the structuring of the metal conductor tracks of all of the metallizing planes, a so-called annealing process step is typically performed. That is understood to mean a tempering process which can optionally be performed in an atmosphere that can contain H
2
. As a result, surface states can be saturated, thus reducing leakage currents.
In some cases, an annealing process step is also necessary after the structuring of the metal conductor tracks, to prevent the formation of voids in the metal. It is also possible for the annealing process step to be necessary not because of the H
2
diffusion, but only because of its positive influence on avoiding the creation of the voids.
However, the disadvantage of such annealing process steps is that they require a very long process time and thus lengthen the total processing time considerably, since loading and unloading the process chambers takes a very long time.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for improving the quality of metal conductor tracks on semiconductor structures, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type, in which the creation of voids is prevented and with which a considerable shortening of the process time can be achieved.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for improving the quality of metal tracks on wafers, which comprises depositing and structuring metallizing planes;
subsequently depositing an interlevel dielectric covering each of the metallizing planes; and performing an integrated annealing and tempering step at an onset of the step of depositing the interlevel dielectric.
A considerable reduction in the total process time can be achieved by the invention by eliminating the separate metal annealing process step. It is especially advantageous if the annealing or tempering step is integrated with the deposition process for the subsequent forming of the interlevel dielectric. To that end, immediately before the deposition of the interlevel dielectric, the metal conductor tracks are thermally treated, and voids are, for instance, avoided. The metal conductor tracks, having properties which are improved, thus also form a better basis for the deposition of the interlevel dielectric.
In accordance with another mode of the invention, in a first partial step of the deposition of the interlevel dielectric, the wafer is heated to the annealing temperature, so that the granular structure of the metal can be converted in the same way as in a pure annealing step.
In accordance with a further mode of the invention, in a second partial step, the deposition of the interlevel dielectric takes place after the annealing step and after the cooling down of the wafer. In a variant of the method, in the second partial step after the annealing step, the wafer can be tempered to the temperature required for the oxide deposition, after which the interlevel dielectric deposition is then carried out. In both cases, a considerable shortening of the total process time is achieved. Furthermore, a variation in the oxide deposition is avoided in this way.
In accordance with an added mode of the invention, the heating of the wafer to the temperature required for the annealing step is indirectly performed by radiant heating. Heating the wafer in a CVD system, which is required anyway for the subsequent deposition of the interlevel dielectric, can preferably be performed by ignition of a non-directional plasma. The non-directional plasma is generated by its ignition without the application of a bias voltage.
In accordance with a concomitant mode of the invention, the integrated annealing step takes place in an atmosphere that contains H
2
.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for improving the quality of metal conductor tracks on semiconductor structures, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 5814554 (1998-09-01), De Samber et al.
Werner Kern et al.: “Simultaneous deposition and fusion flow planarization of borophosphosilicate glass in new chemical vapor deposition reactor”, Thin Solid Films, No. 206, 1991, pp. 64-69.
D. Widmann et al.: “Technologie hochintegrierter Schaltungen” [technology of highly integrated circuits ]in W. Heywang et al. (ed.): “Halbleiterelektronik”, [semiconductor electronic], vol. 19, Berlin, Springer Verlag, 1996, pp. 13-40.
International Publication No. WO 96/12295 (Myers et al.), dated Apr. 25, 1996.
International Publication No. WO 97/12399 (Rastogi et al.), dated Apr. 3, 1997.
Collins D. M.
Picardat Kevin M.
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