Single step etched moat

Details Single step etched moat Single step etched moat

2000-11-08

2002-03-26

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C257S107000

Reexamination Certificate

active

06362112

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices and methods of manufacturing semiconductor devices and, more particularly, to edge terminations of and methods for forming edge terminations of semiconductor devices by etching moats between individual devices formed on wafers.
BACKGROUND OF THE INVENTION
Semiconductor devices are commonly formed by subjecting wafers of semiconductor material to several processing steps in which various layers and coatings are applied to the wafer. After the desired layers have been applied to the wafer, it is a common practice, particularly in the power semi-conductor business, that moats are etched in the surface of the wafer to separate and define the individual devices. Etching the moats is also one of the steps in forming the edge terminations of the devices.
Failure in semiconductor devices commonly occurs at the edge terminations of the devices where the moats are etched. Such failures are caused by electric field magnitudes that are too large for the edge of the devices. To minimize these failures, edge termination configurations and methods of forming the edge terminations have been developed. Generally, it is advantageous to maximize the length of the edge terminations in the regions of the high resistivity layers of the devices. By maximizing this distance the electric field magnitudes at the edges of the devices is minimized. To increase these distances, methods have employed multiple etching steps thereby controlling the configurations of the edge terminations to maximize the edge termination lengths. While these methods are generally effective to maximize the distances with the desired result of minimizing edge termination failures, the multiple etching steps substantially increase the cost of and time required for manufacturing the devices.
BRIEF SUMMARY OF THE INVENTION
There is, therefore, provided in the practice of the invention a novel method for etching a moat to define semiconductor devices with etched terminations. The method comprises forming a wafer semiconductor material having multiple layers for forming desired semiconductor devices, and masking a surface of the wafer with a mask which includes a plurality of gridlines and at least one grid ring.
In a preferred embodiment, the moat is etched in a single step through a mask having a grid of intersecting and interconnected gridlines and a plurality of grid rings separated from the grid lines by the edge termination etching shields. Preferably, one grid ring is positioned within each device area. As the moat is etched in a single step, grid ring divots are formed beneath the grid rings and grid line divots are formed beneath the grid lines. The ring divots have a ring depth, which increases as the surface of the wafer is etched, and the line divots have a line depth increasing faster than the ring depth as the moat is etched. When the etching process is completed, the line depth is greater than the ring depth. To obtain the variation in depth, the grid rings have a ring width, which is less than a grid line width of the grid lines.
The invention is further directed to a moat mask used in the method for etching the moat. The moat mask includes a grid having a plurality of grid lines corresponding to lines of separation defining a plurality of device areas bounded by the lines of separation for the devices. At least one grid ring is positioned within one of the device areas.
In a preferred embodiment, the mask is created with a layer of photoresist applied to a surface of a wafer. The pattern of grid lines and grid rings creates a plurality of device area etching shields and a plurality of edge termination etching shields spaced from the device area etching shields. In the method, these etching shields are formed on the surface of the wafer.
The invention is further directed to wafers and electrical devices and components formed by these methods.
Accordingly, it is the object of the present invention to provide an improved method for etching a moat to define semiconductor devices with long edge terminations.
It is a further object of the present invention to provide an improved moat mask for forming long edge terminations in substantially a single step.


REFERENCES:
patent: 5148241 (1992-09-01), Sugita
patent: 5278443 (1994-01-01), Mori et al.
patent: 5291051 (1994-03-01), Hoang et al.
patent: 5914500 (1999-06-01), Bakowski et al.
patent: 5949124 (1999-09-01), Hadizad et al.
patent: 6110763 (2000-08-01), Temple
patent: 6204097 (2001-03-01), Shen et al.

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