Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-10-06
2002-05-14
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C361S792000
Reexamination Certificate
active
06388202
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to printed circuit boards, and in particular to high density multi-layer printed circuit boards.
BACKGROUND
Historically, multi-layer printed circuit boards have been fabricated by laminating sequential layers of dielectric material and forming circuit patterns on each layer. The various layers of circuitry are interconnected by mechanically drilling holes and plating. This technology has run into the limitation of cost and size, as it is very difficult and expensive to drill a hole much smaller than about 0.25 mm. A new technology known as High Density Interconnect (HDI) technology circumvents this problem by using alternative methods to form the holes connecting the various layers. HDI technologies are lumped into three major categories based on the method used to form the holes (vias)—(1) plasma via, (2) laser via, and (3) photo via. Each of the technologies has certain advantages and disadvantages. For example, with plasma via technology the capability exists to use a variety of materials, such as epoxy or polyimide, as the dielectric layer. However, the via size that is capable of being formed is large and limited to holes greater than 0.15 mm to 0.20 mm. Laser via technology also employs a variety of dielectric materials such as epoxy, polyimide, polyfluorocarbons, aramid, etc., thus enabling the selection of a dielectric material with various electronic properties such as low loss factor and low or high dielectric constant. Additional benefits of laser processing are small via sizes (0.05 mm) and dielectric thickness up to 0.1 mm is possible. However, laser processing is not the most economical method to fabricate circuits, because, as in mechanical drilling, the vias are formed individually, there is a high cost associated with producing large quantities of vias. Forming vias by laser drilling is a single sided process, so when vias are needed on opposite sides of the printed circuit board there is a significant cost adder. Photo via technology is capable of producing very small vias (<0.05 mm) and since all the vias are formed simultaneously, it is the most cost effective. However, the choice of dielectric materials is limited, and the dielectric thickness is limited to a maximum of approximately 0.05 mm. This can be a problem for providing adequate isolation between adjacent layers for certain radio frequency (RF) and high speed digital applications. Printed circuit boards which are used in wireless communications equipment carry circuitry used for both RF and high speed digital signals and also for logic, microprocessor, and other controller-type functions. However, the requirements for the circuitry associated with each is different. Microprocessor applications require high density interconnections on the circuit board, and a photo via technology works best here because it provides the highest interconnection capability for the lowest price. Also, the limitations of the dielectric material do not negatively impact performance. On the other hand, RF type circuitry for voltage controlled oscillators, synthesizers, etc. does not require high density circuitry for interconnection but does require precisely controlled impedance matching for critical signal paths.
To meet these requirements and to provide the size reduction which conventional multi-layer lamination/drilling technology is not capable of, laser vias work best. The laser via process enables utilization of materials which have optimal electrical performance and the added thickness enables a significant increase in layer to layer electrical isolation. However, the laser processing needed to produce the small via size has the penalty of increased cost. Clearly, an improvement in the art is needed to overcome these various disadvantages.
REFERENCES:
patent: 4668332 (1987-05-01), Ohnuki et al.
patent: 5451721 (1995-09-01), Tsukada et al.
patent: 5487218 (1996-01-01), Bhatt et al.
patent: 8-8541 (1996-01-01), None
Arledge John K.
Barreto Joaquin
Swirbel Thomas J.
Dorinski Dale W.
Garrett Scott M.
Motorola Inc.
Paladini Albert W.
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