Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
1999-12-17
2002-03-19
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S075000, C438S147000
Reexamination Certificate
active
06358768
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state image sensor and, more particularly, to a solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency.
2. Discussion of the Related Art
FIG. 1
is a layout of a general solid-state image sensor which includes a plurality of photo diode (PD) regions for converting a light signal into an electric signal charge, vertical charge coupled device (hereinafter referred to as VCCD) regions formed at right angle to the PD regions for transferring in a vertical direction the electric signal charge converted by the PD regions, a HCCD formed at right angle to the VCCDs for transferring in a horizontal direction the signal charge transferred from the VCCDs, and a sensing amplifier SA for sensing the signal charge transferred from the HCCD.
In such a solid-state image sensor having the aforementioned structure, since the HCCD must read charges in parallel transferred from VCCDs in a very short time the corresponding, clocking should be carried out Accordingly, a 2-phase clocking is carried out on average in an HCCD unlike VCCDs in which a 4-phase clocking is carried out.
A conventional HCCD will be described with reference to the accompanying drawings.
FIG. 2A
is a cross-sectional view of a conventional HCCD and
FIG. 2B
is a potential profile of a conventional HCCD.
As shown in
FIG. 2A
, a HCCD includes a p-type well
13
formed on an N-type semiconductor substrate
11
, a buried charge coupled device (hereinafter referred to as BCCD)
15
formed on a predetermined area of the p-type well
13
, a gate insulating layer
17
formed on the BCCD
15
, first and second polygate electrodes
19
and
19
a
formed alternately and insulatively on the gate insulating layer
17
, and buried regions
21
formed under the second polygate electrodes
19
a
for potential difference between the second polygate electrodes
19
a
and the BCCD
15
. At this time, a gate insulating layer
17
a
is formed between the first and second polygate electrodes
19
and
19
a.
In this HCCD, with potential wells maintained in a form of stairs as shown in
FIG. 2B
, charges are moved in a specific direction. To describe in more details, when t=1, charges gather at the bottom of the potential well of a fourth polygate electrode which a high voltage is applied to. When t=2, a high voltage is applied to the first and second polygate electrodes, whereby energy levels at the bottoms of the first and second polygate electrodes decrease; and a low voltage is applied to the third and fourth polygate electrodes, whereby energy levels at their bottoms rise. However, electrons which gather at the bottom of the fourth polygate electrode can not move left because of a barrier region
21
under the third polygate electrode. As energy levels of fifth and sixth polygate electrodes decrease gradually such that a right energy barrier of the fifth polygate electrode is removed, charges moved toward the bottom of the fifth and sixth polygate electrodes having low energy levels. If the energy levels of the fifth and sixth polygate electrodes become high enough, potential walls having a form of stairs are formed such that the electrons-gathering position turns from the bottom of the fourth polygate electrode to that of the eighth polygate electrode. As previously described, potential levels change sequentially by using the conventional
2
-phase clocking, thereby moving signal charges toward the sensing amplifier.
However, such a conventional solid-state image sensor has the following problems. Since the potential difference is achieved after formation of a first polygate electrode, an ion-implanting process step is performed with the first polygate electrode serving as a mask. Further, since another process step is necessary for forming a second polygate electrode, the entire process is very complex.
SUMMERY OF THE INVENTION
Therefore, the present invention is directed to a solid-state image sensor and a fabricating method thereof that substantially obviate one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a solid-state image sensor and a fabricating method thereof in which, instead of performing an ion-implanting process for generating the potential difference, polygate electrodes having different lengths are formed to generate the necessary potential difference, thus simplifying the entire process.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a solid-state image sensor having an HCCD and VCCDs includes a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.
In another aspect of the present invention, a method for fabricating a solid-state image sensor having an HCCD and VCCDs includes the steps of forming a well region of a second conductivity type formed on a semiconductor substrate of a first conductivity type; forming a HCCD of the first conductivity type on the well region; forming a gate insulating layer on the HCCD and then a polysilicon layer on the gate insualting layer; and patterning the polysilicon layer to form a plurality of polygate electrodes having lengths decreasing toward a charge-moving direction.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5289022 (1994-02-01), Iizuka et al.
patent: 5406101 (1995-04-01), Park
patent: 5760430 (1998-06-01), Kato
patent: 5891752 (1999-04-01), Losee
patent: 5895944 (1999-04-01), Yamada
patent: 6114717 (2000-09-01), Uchiya
“A 1-Megapixel, Progressive-Scan Image Sensor With Antiblooming Control and Lag-Free Operation,” IEEE Transactions on Electron Devices, vol. 38, No. 5, May 1991, pp. 981-988.
Moon Sang Ho
Park Yong
Chaudhuri Olik
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Pham Hoai
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