Patent
1995-03-28
1998-09-01
Teska, Kevin J.
395441, 395275, 395733, G06F 1300, G06F 1312
Patent
active
058023453
ABSTRACT:
A computer system which includes a host machine having a memory and a CPU with an interrupt handling feature, an auxiliary memory unit for recording and reproducing data and an input/output unit for permitting data input and output between the host machine and the auxiliary memory unit. The CPU of the host machine generates a plurality of commands for designating access to the auxiliary unit, in response to at least one command, groups a plurality of the commands for designating access to the auxiliary memory unit, into at least one group and supplies the input/output unit with the commands independently of one another. The input/output unit executes access to the auxiliary memory unit as designated by each of the commands of one group supplied independently of one another by the CPU, and notifies the CPU by a single interruption that execution of the commands of the one group has been terminated when the accesses designated by all commands belonging to the one group have been terminated.
REFERENCES:
patent: 5148432 (1992-09-01), Gordon et al.
patent: 5179704 (1993-01-01), Jibbe et al.
patent: 5313588 (1994-05-01), Nagashige et al.
patent: 5572699 (1996-11-01), Kamo et al.
Arakawa Hiroshi
Kan Masayuki
Kaneda Yasunori
Matsunami Naoto
Oeda Takashi
Siek Vuthe
Teska Kevin J.
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