Pipeline throughput via parallel out-of-order execution of adds

Details Pipeline throughput via parallel out-of-order execution of adds Pipeline throughput via parallel out-of-order execution of adds

1997-02-14

1998-09-01

Lim, Krisna

395392, 395394, G06F 930, G06F 938

Patent

active

058023399

ABSTRACT:
The existing execution units of a high-performance processor are augmented by the addition of a supplemental integer execution unit, termed the Add/Move Unit (AMU), which performs select adds and moves in parallel and out-of-order with respect to the other execution units. At small incremental cost, AMU enables better use of the expensive limited resources of an existing Address Preparation unit (AP), which handles linear and physical address generation for memory operand references, control transfers, and page crosses. AMU removes data dependencies and thereby increases the available instruction level parallelism. The increased instruction level parallelism is readily exploited by the processor's ability to perform out-of-order and speculative execution, and performance is enhanced as a result.

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patent: 5487156 (1996-01-01), Popescu et al.
patent: 5628021 (1997-05-01), Jadonato et al.
patent: 5632023 (1997-05-01), White et al.

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