Methods of bonding two semiconductor devices

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S613000, C257S738000, C257S778000, C228S180210, C228S180220

Reexamination Certificate

active

07378297

ABSTRACT:
A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

REFERENCES:
patent: 5641113 (1997-06-01), Somaki et al.
patent: 5844315 (1998-12-01), Melton et al.
patent: 6168972 (2001-01-01), Wang et al.
patent: 6229158 (2001-05-01), Minemier et al.
patent: 6425516 (2002-07-01), Iwatsu et al.
patent: 6555917 (2003-04-01), Heo
patent: 6664637 (2003-12-01), Jimarez et al.
patent: 6787917 (2004-09-01), Lee et al.
patent: 6908784 (2005-06-01), Farnworth et al.
patent: 7122906 (2006-10-01), Doan
patent: 7205177 (2007-04-01), De Raedt et al.
patent: 2002/0195703 (2002-12-01), Kameda
patent: 2005/0017336 (2005-01-01), Kung et al.
patent: 0 729 182 (1996-08-01), None
patent: 0 875 935 (1998-11-01), None
patent: 1 489 657 (2004-12-01), None
patent: 2004265888 (2004-09-01), None
patent: WO 99/04430 (1999-01-01), None
Keser et al., “Encapsulated Double-Bump WL-CSP: Design and Reliability,”2001 Electronic Components and Technology Conference.
Beyne, “3D Interconnection and Packaging: 3D-SIP, 3D-SOC or 3D-IC?,” IMEC, Belgium.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of bonding two semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of bonding two semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of bonding two semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2812854

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.