Filtering, equalization, and power estimation for enabling...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07346638

ABSTRACT:
A power spectrum estimator consistent with certain embodiments has a pulse extraction circuit that compares a digital input signal with a delayed version of the digital input signal to produce an output signal containing extracted pulses. An averaging circuit receives the output pulse and produces therefrom an averaged signal representing the averaged value of the output signal. A subtracter subtracts a reference signal from the averaged signal to produce a difference signal. An absolute value circuit converts the difference signal to an error signal by taking the absolute value of the difference signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

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patent: 6073152 (2000-06-01), De Vries
patent: 7010226 (2006-03-01), Le Sauze et al.
patent: 7023981 (2006-04-01), Stephens et al.
patent: 2004/0039763 (2004-02-01), Koizumi et al.
“Pulse Extraction: A Digital Power Spectrum Estimation Method for Adaptation of Gbps Equalizers”, by Xiaofeng Lin, et al, Proceedings of the IEEE International Symposium on Circuits and Systems, May 25-28, 2003.
“A CMOS Analog Continuous-Time FIR Filter for 1Gbps Cable Equalizer”, by Xiaofeng Lin, et al, Proceedings of the IEEE International Symposium on Circuits and Systems, May 25-28, 2003.

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