Low power high density random access memory flash cells and...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185290

Reexamination Certificate

active

07324387

ABSTRACT:
Low power high density random access memory flash cells and arrays using Fowler Nordheim (FN) tunneling for both programming and erasing. The memory array is divided into sectors, each sector comprising a predetermined number of rows. The bit lines are similarly segmented, each global bit line being selectively connectable to a local bit line for each sector, each local bit line being connected to the drains of all floating gate cells in a respective column of each sector. The sources of all floating gate cells in a respective column of each sector are connected to a local source line for that sector, the local source lines for each sector being controllably connectable to respective global source lines. Consequently all floating gate cells within a column of a sector are connected in parallel, source to source and drain to drain. Representative programming and erase voltages not disturbing other cells are disclosed.

REFERENCES:
patent: 5946232 (1999-08-01), Yoon
patent: 5964232 (1999-10-01), Chung
patent: 6262914 (2001-07-01), Smayling et al.
patent: 6498752 (2002-12-01), Hsu et al.
patent: 6628563 (2003-09-01), Hsu et al.
patent: 7177199 (2007-02-01), Chen et al.
patent: 2002/0196696 (2002-12-01), Chevallier et al.

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