Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-07-22
2008-07-22
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185130, C365S185110
Reexamination Certificate
active
07403427
ABSTRACT:
In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, the method comprising the steps of: raising the erase pulse voltage to a first intermediate voltage less than a target erase pulse voltage; maintaining the erase pulse voltage at the first intermediate voltage for a first period of time; after the first time period, raising the erase pulse voltage to the target erase pulse voltage; and maintaining the erase pulse voltage at the target erase pulse voltage during an erase operation.
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Kang-Deog Suh et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995.
Duane Morris LLP
Elite Semiconductor Memory Technology Inc.
Nguyen Dang T
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