Semiconductor device with isolation trench liner, and...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S436000, C438S437000, C438S424000, C257S510000, C257SE21546

Reexamination Certificate

active

07998832

ABSTRACT:
A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

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patent: 2005098923 (2005-10-01), None
International Search Report for PCT/US2009/053271 mailed Nov. 2, 2009.

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