Multiplexer cell and multiplexer circuit arrangement and...

Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S538000

Reexamination Certificate

active

07349449

ABSTRACT:
A multiplexer cell (1) for converting an input signal (D0, D1) with a data input rate (fD) into an output signal (E) with a data output rate (fE), which in particular is twice the size of the data input rate, is proposed. For this purpose the multiplexer cell (1) according to the invention has a clock input connection (6) for supplying a clock signal (C0), the frequency of which is the same as the data input rate (fD), a first and a second data input connection (2, 4) for supplying a first or second input signal (D0, D1) at the data input rate (fD), a data output connection (6) for the output of the output signal (E) at the data output rate (fE), a first and a second master-slave register circuit (22, 24), the inputs of which are connected to the first or second data input connection (2, 4) and the clock inputs of which are connected to the clock input connection (6), for the flank controlled output of the first or second input signal (D0, D1), a delay circuit (18) the input of which is connected to the output of the second master-slave register circuit (24) and the clock input of which is connected to the clock input connection (6), for the delayed output of the second input signal (D1), wherein the delay is half a clock period of the clock signal (C0) and an XOR gate circuit (20), the first input of which is connected to the output of the first master-slave register circuit (22), the second input of which is connected to the output of the delay circuit (18) and the output of which is connected to the data output connection (8).

REFERENCES:
patent: 5818366 (1998-10-01), Morley
patent: 6999407 (2006-02-01), Moon
patent: 43 05 677 (1993-08-01), None
patent: 199 52 370 (2001-05-01), None
Tanabe, et al.,IEEE Journal of Solid-State Circuits, Vo. 36, No. 6, pp. 988-996 (Jun. 2001).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multiplexer cell and multiplexer circuit arrangement and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplexer cell and multiplexer circuit arrangement and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexer cell and multiplexer circuit arrangement and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2796218

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.