Semiconductor device including interconnects formed by...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S759000, C257S760000, C257S700000, C257S774000, C257S751000, C257SE21579, C257SE21577, C438S622000

Reexamination Certificate

active

07361992

ABSTRACT:
After etching the interlayer dielectric film4formed on the lower layer interconnect line1into a shape with holes, the upper layer dielectric film6is etched into a shape with trenches utilizing the etching stopper5. The etching stopper5which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film4which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal10.

REFERENCES:
patent: 6218287 (2001-04-01), Matsumoto
patent: 6225207 (2001-05-01), Parikh
patent: 6603204 (2003-08-01), Gates et al.
patent: 6764810 (2004-07-01), Ma et al.
patent: 2002/0008323 (2002-01-01), Watanabe et al.
Chinese Office Action issued in corresponding Chinese Patent App. No. 03143451.7, dated Aug. 18, 2006.
Chinese Office Action, Date of Dispatch: Feb. 24, 2006.

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