Multiplex communications – Wide area network – Packet switching
Patent
1995-08-03
1998-09-01
Kim, Kenneth S.
Multiplex communications
Wide area network
Packet switching
370230, 370235, 370395, 39520068, H04L 1200
Patent
active
058022872
ABSTRACT:
An asynchronous transfer mode (ATM) processing system interconnection or termination unit is implemented on a single integrated circuit chip. The unit includes a universal protocol device having Virtual Channel Memory (VCR) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for interconnecting the VCR to a host unit, and a Parallel Cell Interface (PCI) for interconnecting the VCR to an ATM network. A Reduced Instruction Set Computer (RISC) microprocessor controls the DMA controller as well as segmentation and reassembly of Conversion Sublayer Payload Data Unit (CS-PDU)s and transfer between the memory, the host and the ATM network and other operations of the device using single clock cycle instructions. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which is downloaded at initialization. The program can be user designed to accommodate changes in ATM network protocols and congestion handling routines. A Pacing Rate Unit (PRU) includes a global pacing rate register which automatically reduces the maximum transmission rate of ATM cells in response to a sensed congestion condition in the ATM network.
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Tanenbaum Structured Computer Organization pp. 10-12 1984.
Bergantino Paul
Rostoker Michael D.
Stelliga D. Tony
Kim Kenneth S.
LSI Logic Corporation
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