Method for forming a shallow trench isolation structure with...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C257SE21549

Reexamination Certificate

active

07314809

ABSTRACT:
A method for forming a shallow trench isolation (STI) structure with reduced stress is described. An amorphous silicon layer is deposited on a trench surface of a shallow trench isolation structure, and the amorphous silicon is then oxidized by thermal oxidation to form a liner oxide. The thickness of the liner oxide is uniform to reduce stress caused by a liner oxide having non-uniform thickness in the prior art, and the leakage risk between the semiconductor devices can thus be prevented.

REFERENCES:
patent: 6468853 (2002-10-01), Balasubramanian et al.
patent: 2003/0040189 (2003-02-01), Chang et al.
patent: 2003/0207591 (2003-11-01), Lu et al.
patent: 2004/0240822 (2004-12-01), Patel et al.
patent: 2005/0020043 (2005-01-01), Lai
patent: 2005/0186755 (2005-08-01), Smythe et al.

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