1996-12-17
1998-09-01
Treat, William M.
39518306, G06F 1134
Patent
active
058022732
ABSTRACT:
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
REFERENCES:
patent: 5564015 (1996-10-01), Bunnell
patent: 5594864 (1997-01-01), Trauben
patent: 5691920 (1997-11-01), Levine et al.
Welbon, E.H., et al., "Load Miss Performance Analysis Methodology Using the Power PC 604 Performance Monitor for OLTP Workloads, Digest of Papers. COMPCON'96.
Technologies for the Information Superhighway, Forty-First IEEE Computer Society International Conference (Cat. No. 96CB35911), Feb. 25-28, 1996, pp. 111-116.
Performance Monitor, PowerPC 604 RISC Microprocessor User's Manual, Chapter 9, pp. 9-1 through 9-11, IBM 1994.
Levine Frank Eliot
Moore Roy Stuart
Roth Charles Philip
Welbon Edward Hugh
International Business Machines - Corporation
Kordzik Kelly K.
McBurney Mark E.
Treat William M.
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