Method and apparatus for signaling characteristics of a...

Pulse or digital communications – Synchronizers

Reexamination Certificate

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C375S364000

Type

Reexamination Certificate

Status

active

Patent number

07379517

Description

ABSTRACT:
A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300and400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.

REFERENCES:
patent: 5631928 (1997-05-01), Hossner
patent: 5760717 (1998-06-01), Scholz
patent: 6850649 (2005-02-01), Malvar
patent: 6930619 (2005-08-01), Shim et al.
patent: 2004/0130467 (2004-07-01), Nakagawa et al.
Kamran Iravani et al.; “Clock and Data Recovery for 1.25Gb/s Ethernet Transceiver in 0.35um CMOS”; IEEE 1998 Custom Integrated Circuits Conference; pp. 261-264.
Kamran Iravani and Gary Miller; “VCOs with Very Low Sensitivity to Noise on the Power Supply”; IEEE 1998 Custom Integrated Circuits Conference; pp. 515-518.
Alan Fiedler et al.; FP 15.1: A 1.0625Gbps Transeiver with 2x-Oversampling and Transmit Signal Pre-Emphasis; ISSCC97/Session 15/ Serial Data Communications/Paper FP 15.1; 1997 IEEE International Solid-State Circuits Conference; pp. 238-239 and 464.
Lizhong Sun et al; “A 1.25GHz 0.35um Monolithic CMOS PLL Clock Generator for Data Communications”; IEEE 1998 Custom Integrated Circuits Conference; pp. 265-268.
Joonsuk Lee et al.; “WA 20.1 A 250MHz Low Jitter Adaptive Bandwidth PLL”; 1999 IEEE International Solid-State circuits Conference; ISSCC99 / Session 20 /Paper WA 20.1; Copyright IEEE; pp. 346-347 and 477.
Richard C. Walker et al.; SA 19:1: A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission; ISSCC98 / Session 19 / Multi-Gigahertz Serial Data / Paper SA 19.1; 3 pgs.
M. Fukaishi et al.; SA 19.3: “A 4.25Gb/s CMOS Fiber Channel Transceiver with Asynchronous Bianry Tree-type Demultiplexer and Frequency Conversion Architecture”; ISSCC98 / Session 19 / Multi-Gigahertz Serial Data / Paper SA 19.3; 3 pgs.
Dao-Long Chen et al.; FP 15.3: “A 1.25Gb/s, 460mW CMOS Transceiver for Serial Data Communication”; ISSCC97 / Session 15 / Serial Data Communications / Paper FP 15.3; pp. 242-243 and 465.
B. Lau et al.; FA 10.4: “A 2.6GB/s Multi-Purpose Chip-to-Chip Interface”; ISSCC98 / Session 10 / High-Speed Chip-to-Chip Connections / Paper FA 10.4; pp. 162-163 and 431.
Hirotaka Tamura et al.; FA 10.5: “PRD-Based Global-Mean-Time Signaling for High-Speed Chip-to-Chip Communications”; ISSCC98 / Session 10 / High-Speed Chip-to-Chip Connections / Paper FA 10.5; pp. 164-165.
Ramin Farjad-Rad et al.; “A 0.4-um CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter”; Copyright 1999 IEEE; IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999; pp. 580-585.
Ramin Farjad-Rad et al.; “A 0.4-um CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter”; 1999 Symposium on VLSI circuits Digest of Technical Papers; Copyright 1998 IEEE; pp. 198-199.
David A. Johns and Daniel Essig; “Integrated Circuits for Data Transmission Over Twisted-Pair Channels”; IEEE Journal of Solid-State Circuits, vol. 32, No. 3, Mar. 1997; Copyright 1997 IEEE; pp. 398-406.
Liang Dai and Ramesh Harjani; “Comparison and Analysis of Phase Noise in Ring Oscillators”; ISCAS 2000—IEEE International Symposium on Circuits and System, May 28-31, 2000; Geneva, Switzerland; Copyright 2000 IEEE; pp. V-77 to V-80.
Payam Heydari and Massoud Pedram; “Analysis of Jitter Due to Power-Supply Noise in Phase-Locked Loops”; IEEE 2000 Custom Integrated Circuits Conference; Copyright 2000 IEEE; pp. 443-446.
A. Mouaki Benani and F. Gagnon; “Comparison of Carrier Recovery Techniques in N-QAM Digital Communications Systems”; Copyright 1999 IEEE; pp. 73-77.
Ali Hajimiri et al.; “Jitter and Phase Noise in Ring Oscillators”; IEEE Journal of Solid-State Circuits, vol. 34, No. 6, Jun. 1999; Copyright 1999 IEEE; pp. 790-804.
Masayuki Takahashi et al.; “VCO Jitter Simulation and Its Comparison with Measurement”; Copyright 1999 IEEE; pp. 85-88.
Apler Demir et al.; “Modeling and Simulation of Noise in Analog/Mixed-Signal Communication Systems”; Copyright 1999 IEEE; IEEE 1999 Custom Integrated Circuits Conference; pp. 385-392.
Min-ho Kim et al.; “A VCO Jitter Performance Comparison of Frequency Synthesizer with Analog-HDL and SPICE Modeling”; Copyright 1999 IEEE; 1999 IEEE Tencon; pp. 1034-1037
Thomas H. Lee; “Oscillator Phase Noise: A Tutorial (Invited)”; Copyright 1999 IEEE; IEEE 1999 Custom Integrated Circuits Conference; pp. 373-380.
Ali Hajimiri et al.; “Design Issues in CMOS Differential LC Oscillators”; Copyright 1999 IEEE; IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999; pp. 717-724.
HongMo Wang; “Comments on “Design Issues in CMOS Differential LC Oscillators ””; Copyright 2000 IEEE; IEEE Transactions on Solid State Circuits, vol. 35, No. 2, Feb. 2000; pp. 286-287.
Ali Hajimiri et al.; “Phase Noise in CMOS Differential LC Oscillators”; Copyright 1998 IEEE; 32 pages.
Ali Hajimiri et al.; “Phase Noise in Multi-Gigahertz CMOS Ring Oscillators”; available from http://smire.stanford.edu/papers/CICC98p-ali.pdf; 32 pages.
Ramin Farjad-Rad et al.; “A 0.3-um CMOS 8-Gb/s 4-PAM Serial Link Transceiver”; Copyright 2000 IEEE; IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000; pp. 757-764.

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