Clustered superscalar processor with communication control...

Details Clustered superscalar processor with communication control... Clustered superscalar processor with communication control...

2008-05-13

2008-05-13

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S023000

Reexamination Certificate

active

07373485

ABSTRACT:
A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the instruction that will be stored in the instruction window and a previous instruction stored in the instruction window. When there is a data dependency relationship, the execution result of the previous instruction of one cluster is communicated to a register cache of another cluster that executes the instruction having a data dependency relationship with the previous instruction.

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S. Palacharla, N.P. Jouppi, and J.E. Smith, “Complexity-Effective Superscalar Processors,” Proceedings of 24thInternational Symposium on Computer Architecture, pp. 206-218, Jun. 1997.
J.L. Cruz, A. Gonzalez, M. Valero, and N.P. Tophan, “Multi-Banked Register File Architectures,” Proceedings of 27thInternational Symposium on Computer Architecture, pp. 316-325, Jun. 2000.

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