Multi-level nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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Details

C365S185190, C365S185170, C365S185220, C365S185210

Reexamination Certificate

active

07995389

ABSTRACT:
A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials.

REFERENCES:
patent: 6434055 (2002-08-01), Tanaka et al.
patent: 7359245 (2008-04-01), Kim et al.
patent: 7369437 (2008-05-01), Kamei
patent: 7529131 (2009-05-01), Iwai et al.
patent: 2004/0109357 (2004-06-01), Cernea et al.
patent: 2009/0073763 (2009-03-01), Hosono

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