System and method for multi-channel delay cell based clock...

Details System and method for multi-channel delay cell based clock... System and method for multi-channel delay cell based clock...

2008-03-11

2008-03-11

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S147000

Reexamination Certificate

active

07342521

ABSTRACT:
Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed clock signal based on the reference clock signal. A dynamic link library clock and data recovery module reads and writes data flows contained within serialized data onto parallel data paths at a modified high speed clock signal based on the reference high speed clock signal.

REFERENCES:
patent: 5953386 (1999-09-01), Anderson
patent: 6624766 (2003-09-01), Possley et al.
patent: 6628214 (2003-09-01), Kawase et al.
patent: 6707399 (2004-03-01), Wang et al.
patent: 6911923 (2005-06-01), Wang et al.
patent: 7031421 (2006-04-01), Marx et al.
patent: 2002/0064175 (2002-05-01), Traverso et al.
patent: 2002/0075981 (2002-06-01), Tang et al.
patent: 2005/0040876 (2005-02-01), Jeon

Affiliated with

Also associated with

Rating

System and method for multi-channel delay cell based clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for multi-channel delay cell based clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for multi-channel delay cell based clock... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2786332