Wafer having a dicing area having a step region covered with a c

Details Wafer having a dicing area having a step region covered with a c Wafer having a dicing area having a step region covered with a c

1989-07-27

1990-10-30

Hille, Rolf

357 55, 357 56, 357 71, H01L 2348, H01L 2346, H01L 2962, H01L 2944

Patent

active

049672592

ABSTRACT:
A conductive layer is formed at the step portion in a dicing line formed vertically and horizontally on a wafer and at a step portion of the region on which a test element for processing control formed inside of the dicing line or an alignment mark are formed, so as to completely cover the step portions. Since the conductive layer does not come off the step portions in subsequent steps, a short circuit of a wiring layer formed on a semiconductor chip region is prevented.

REFERENCES:
patent: 4142160 (1979-02-01), Tsukada et al.
patent: 4179794 (1979-12-01), Kosugi et al.
patent: 4243997 (1981-01-01), Nazori et al.
patent: 4536950 (1985-08-01), Sadamatsu et al.
patent: 4539742 (1985-09-01), Kanzaki et al.
patent: 4618871 (1986-10-01), Mitlehner et al.
patent: 4683488 (1987-07-01), Lee et al.

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