Vertical dynamic random access memory

Details Vertical dynamic random access memory Vertical dynamic random access memory

1988-12-02

1990-10-30

Munson, Gene M.

357 41, 357 49, 357 55, 357 56, H01L 2978, H01L 2702, H01L 2712, H01L 2906

Patent

active

049672479

ABSTRACT:
A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.

REFERENCES:
patent: 4638460 (1987-01-01), Matsumoto
patent: 4686552 (1987-08-01), Teng et al.
patent: 4704705 (1987-11-01), Womack
patent: 4737829 (1988-04-01), Morimoto et al.
patent: 4833516 (1989-05-01), Hwang et al.
High-Density One-Device Dynamic MOS Memory Cells, by Itoh et al., IEE Proc., vol. 130, Pt. I, No. 3, pp. 127-135, Jun. 1983.
A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell, by Mashiko et al., J. Sol. State Cir., vol. 22, No. 5, Oct. 1987.
Trends in Megabit DRAM Circuit Design, by K. Itoh, Central Research Lab., Hitachi, Ltd., pp. 21-27, 1988.

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