Electrostatic discharge protection in a field programmable...

Details Electrostatic discharge protection in a field programmable... Electrostatic discharge protection in a field programmable...

2011-08-02

2011-08-02

Fureman, Jared (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07990664

ABSTRACT:
An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.

REFERENCES:
patent: 5859758 (1999-01-01), Kim
patent: 6552879 (2003-04-01), Voldman
patent: 7446378 (2008-11-01), Bakker
patent: 2007/0058307 (2007-03-01), Mergens et al.

Affiliated with

Also associated with

Rating

Electrostatic discharge protection in a field programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrostatic discharge protection in a field programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrostatic discharge protection in a field programmable... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2778105