Reconfigurable neural network

Details Reconfigurable neural network Reconfigurable neural network

1991-02-13

1992-03-03

Fleming, Michael R.

Boots, shoes, and leggings

395 27, 364807, 364602, G06F 1518

Patent

active

050939009

ABSTRACT:
Realization of a reconfigurable neuron for use in a neural network has been achieved using analog techniques. In the reconfigurable neuron, digital input data are multiplied by programmable digital weights in a novel connection structure whose output permits straightforward summation of the products thereby forming a sum signal. The sum signal is multiplied by a programmable scalar, in general, 1, when the input data and the digital weights are binary. When the digital input data and the digital weights are multilevel, the scalar in each reconfigurable neuron is programmed to be a fraction which corresponds to the bit position in the digital data representation, that is, a programmable scalar of 1/2, 1/4, 1/8, and so on. The signal formed by scalar multiplication is passed through a programmable build out circuit which permits neural network reconfiguration by interconnection of one neuron to one or more other neurons. Following the build out circuit, the output signal therefrom is supplied to one input of a differential comparator for the reconfigurable neuron. The differential comparator receives its other input from a supplied reference potential. In general, the comparator and reference potential level are designed to generate the nonlinearity for the neuron. One common nonlinearity is a hard limiter function. The present neuron offers the capability of synthesizing other nonlinear transfer functions by utilizing several reference potential levels connected through a controllable switching circuit.

REFERENCES:
patent: 4988891 (1991-01-01), Mashiko
patent: 5021988 (1991-06-01), Mashiko
patent: 5039870 (1991-08-01), Engeler
Schwartz et al., "A Programmable Analog Neural Network Chip", IEEE Jour. Solid State Circuits, vol. 24(3), Apr. 1989, pp. 688-697.
Mead et al., Analog VLSI Implementation of Neural Systems, Klumer Academic Pub., 1989, pp. 135-169.
Rosetto et al., "Analog VLSI Synaptic Matrices as Building Blocks for Neural Networks", IEEE Micro, Dec. 1989, pp. 56-63.
Kub et al., "Programmable Analog Vector-Matrix Multipliers", IEEE Jour. of Solid-State Circuits, vol. 25(1), Feb. 1990, pp. 207-214.
Salam et al., "A Feed Forward Neural Network for CMOS VLSI Implementation", IEEE Midwest Symposium on Circuits and Systems, 1990, pp. 489-492.

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