Method and system for detecting bypass errors in a load/store un

Details Method and system for detecting bypass errors in a load/store un Method and system for detecting bypass errors in a load/store un

1996-01-18

1998-04-07

Swann, Tod R.

395875, 395873, 395471, G06F 1316

Patent

active

057376360

ABSTRACT:
A load queue is provided in a load/store unit of a superscalar processor that includes a real page number buffer for storing a real page number for each instruction entry in the load queue. The load queue also includes a real page number comparator coupled to the real page number buffer for comparing executing load instruction entries with queued load instruction entries in the load queue. The load queue further includes a cache line modified register coupled to the data cache. The cache line modified register marks the queued load instruction entries when a cache line of the data cache addressed by the queued load instruction entry has been modified. In a preferred embodiment, when the executing load instruction is out of program order with respect to one of the queued load instructions, and the modified cache line register has marked the queued load instruction, the load queue signals a sequencer unit to cancel the queued load instruction. The load queue further includes an instruction identification buffer coupled to a sequencer unit for storing an instruction identifier for each entry in the load queue and a program order comparator coupled to the instruction identification buffer. The program comparator compares the ordering of instruction entries in the load queue with the executing load or store instruction.

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