Method and apparatus for dynamic buffer allocation in a bus brid

Details Method and apparatus for dynamic buffer allocation in a bus brid Method and apparatus for dynamic buffer allocation in a bus brid

1996-04-22

1998-09-01

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370413, 395292, 395309, G06F 1300

Patent

active

058020551

ABSTRACT:
A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.

REFERENCES:
patent: 5469435 (1995-11-01), Krein
patent: 5535340 (1996-07-01), Bell
patent: 5546546 (1996-08-01), Bell
patent: 5588125 (1996-12-01), Bennett
patent: 5615343 (1997-03-01), Saraangdhar
patent: 5701422 (1997-12-01), Kirkland, Jr.
patent: 5708794 (1998-01-01), Parks

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